Alps Electric Deploys Berkeley Design Automation Analog FastSPICE™ Platform

AFS Delivers True SPICE Accuracy 5x-10x Faster for Complex Mixed-Signal ICs SANTA CLARA, CA, —August 24, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform) today announced that Alps Electric Co. Ltd., a leading global manufacturer of electronic components for mobile devices, home electronics, automotive vehicles, and industrial [...]
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Berkeley Design Automation Appoints Craig Wentzel VP Worldwide Sales

Veteran EDA and Electronics Industry Executive to Lead Growing Sales Organization SANTA CLARA, CA, — August 17, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform), today announced that Craig Wentzel has joined the company as vice president of worldwide sales. A recognized EDA and electronics industry sales [...]
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SiliconFile Technologies Selects Berkeley Design Automation Analog FastSPICE™ Platform

AFS Delivers 5x-10x Faster Results with Nanometer SPICE Accuracy for Image Sensor ICs SANTA CLARA, CA, — July 27, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform), today announced that SiliconFile Technologies Inc., a leading fabless provider of CMOS image sensors, has selected the AFS Platform for [...]
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Sunplus Technology Deploys Berkeley Design Automation Analog FastSPICE™ Platform

Platform Delivers True SPICE Accurate Device Noise Analysis for Complex Mixed-Signal ICs SANTA CLARA, CA, — May 4, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform, today announced that Sunplus Technology Co. Ltd., one of the world’s leading providers of silicon systems for consumer electronics, has selected the company’s [...]
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Azuro’s Low Power CTS Tool Included in TSMC’s Second Integrated Sign-off Flow Release

Fully scripted grab-it-and-go RTL to GDSII design flow combines PowerCentric with both Cadence and Synopsys P&R tools to deliver seamless integration for clock power reduction Santa Clara, CA – April 12, 2010 – Azuro, Inc., a leading provider of advanced clock tree synthesis and timing optimization tools for digital chip design, today announced the inclusion [...]
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TSMC Certifies Berkeley Design Automation Analog FastSPICE

Analog FastSPICE Meets All TSMC Accuracy and Compatibility Requirements for 28nm LP Technology SANTA CLARA, CA, —April 7, 2010— Berkeley Design Automation Inc., provider of the Analog FastSPICE™ unified circuit verification platform today announced that the Analog FastSPICE™ Platform qualified through TSMC’s SPICE Tool Qualification Program for 28nm low-power (LP) technology. Analog, mixed-signal, and RF [...]
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Berkeley Design Automation and Solido Design Automation Accelerate Nanometer IC Variation Analysis

SANTA CLARA, CA, — January 26, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform), and Solido Design Automation, provider of Variation Designer, today announced a validated flow for rapid reduction in variation risk in nanometer designs at the transistor level. Driven by demand by a leading fabless [...]
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Azuro Closes Fifth Consecutive Year of Revenue Growth

Adds two more top ten semiconductor vendors to list of customers SANTA CLARA, CA – January 19, 2010 – Azuro, Inc., a leading provider of advanced clock tree synthesis and timing optimization tools for digital chip design, today announced that it has completed its fifth consecutive year of revenue growth. Increases in revenue resulted from [...]
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