transistor level statistical design
Berkeley Design Automation and Solido Design Automation Accelerate Nanometer IC Variation Analysis
SANTA CLARA, CA, — January 26, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform), and Solido Design Automation, provider of Variation Designer, today announced a validated flow for rapid reduction in variation risk in nanometer designs at the transistor level. Driven by demand by a leading fabless [...]Read More
Solido Opens SPICE-based Variation Designer Platform for Additional Third-party Integration
Simulator and design environment vendors invited to join Solido Integration Program SAN JOSE, California – January 19, 2010 – Solido Design Automation, a leading developer of software for reducing variation risk in nanometer designs at the transistor level, has opened up its Variation Designer platform for integration into third party simulators and design environments. Variation [...]Read More
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