BDTI Certified Results Show PICO High Level Synthesis Platform Produces Quality of Results Comparable to Hand-coded RTL

Synfora PICO High Level Synthesis Platform Certified in Berkeley Design Technology’s New Tool Certification Program MOUNTAIN VIEW, Calif. – January 18, 2010 – The PICO High Level Synthesis Platform from Synfora, Inc., the premier provider of high level synthesis tools for integrated circuit and system designers, has achieved certification in Berkeley Design Technology, Inc.’s (BDTI’s) [...]
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Synfora Adds Support For Next Generation Xilinx Virtex-6 And Spartan-6 FPGA Devices To PICO Algorithmic Synthesis Tool

Up To 15 Percent Higher Throughput and, Area Reduction Shown In Customer FPGA Designs MOUNTAIN VIEW, Calif. — December 1, 2009 – Synfora, Inc., the premier provider of high level synthesis tools for integrated circuit and system designers of large, complex processing applications, announced a new version of its PICO Extreme™ FPGA C synthesis tool with [...]
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Synfora Acquires Esterel Studio™, Adds Control-Intensive IP Development Capabilities to Product Portfolio

Complementary and Integrated Flow Already in Use by Top Tier Customers MOUNTAIN VIEW, Calif. – August 27, 2009 – Synfora, Inc., the premier provider of algorithmic synthesis tools for integrated circuit and system designers of large, complex processing applications, today announced that it has purchased Esterel Studio™, a tool suite developed by Esterel EDA Technologies. Esterel [...]
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Wavesat Leverages Synfora’s PICO Extreme® for New Wireless SoC Development

Synfora, Inc., the premier provider of algorithmic synthesis tools used to design SoCs and FPGAs, today announced that Wavesat, Inc., a leading provider of broadband wireless silicon solutions, used PICO Extreme® to design a key IP block for the next generation 4G wireless chip, with superb quality of results and extremely short design time.
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Synfora Joins Synopsys System-Level Catalyst Program Synfora Joins Synopsys System-Level Catalyst Program

Synfora, Inc., the premier provider of algorithmic synthesis tools for integrated circuit and system designers of large, complex processing applications, today announced that it has joined the Synopsys System-Level Catalyst Program, which is intended to accelerate the adoption of system-level design and verification tools and methodologies
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