Apache’s Totem-SE Named a Finalist in EDN’S 20th Annual Innovations Awards Competition

SAN JOSE, Calif. – March 1, 2010 - Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced that Totem-SE, the industry’s first fully integrated power and noise analysis platform for analog, mixed-signal, memory, and high-speed I/O designs, has been selected from hundreds of nominations to be [...]
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Apache’s Power and Noise Solutions for Chip-Package-System Convergence Adopted by Sigma Designs for Digital Media SoCs

Contract reflects successful integration of Apache and Sequence Design, now delivering complete power and noise solutions from RTL to GDS SAN JOSE, CALIFORNIA – January 20, 2010 – Apache Design Solutions, the technology leader in power and noise solutions for chip-package-systems (CPS) convergence, today announced that Sigma Designs, Inc. (Nasdaq: SIGM), a leader in digital media [...]
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BDTI Certified Results Show PICO High Level Synthesis Platform Produces Quality of Results Comparable to Hand-coded RTL

Synfora PICO High Level Synthesis Platform Certified in Berkeley Design Technology’s New Tool Certification Program MOUNTAIN VIEW, Calif. – January 18, 2010 – The PICO High Level Synthesis Platform from Synfora, Inc., the premier provider of high level synthesis tools for integrated circuit and system designers, has achieved certification in Berkeley Design Technology, Inc.’s (BDTI’s) [...]
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Oasys Design System Signs WorldWide OEM Agreement to Integrate Concept Engineering’s NlView Visualization Engine

Concept Engineering today announced that Oasys Design Systems, Inc., developer of the RealTime Designer full-chip physical register transfer-level (RTL) synthesis product, has signed a worldwide OEM license for Concept Engineering′s Nlview™ visualization engine
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Synfora Joins Synopsys System-Level Catalyst Program Synfora Joins Synopsys System-Level Catalyst Program

Synfora, Inc., the premier provider of algorithmic synthesis tools for integrated circuit and system designers of large, complex processing applications, today announced that it has joined the Synopsys System-Level Catalyst Program, which is intended to accelerate the adoption of system-level design and verification tools and methodologies
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Satin IP Technologies Helps STMicroelectronics Achieve IP Design Quality Closure

Satin IP Technologies, the company that delivers design quality closure with fast return on investment, has been working with the Home Entertainment and Display (HED) product group of STMicroelectronics on how to monitor and improve the quality of their internally developed semiconductor intellectual property (IP) blocks.
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