Apache’s Totem-SE Named a Finalist in EDN’S 20th Annual Innovations Awards Competition

SAN JOSE, Calif. – March 1, 2010 - Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced that Totem-SE, the industry’s first fully integrated power and noise analysis platform for analog, mixed-signal, memory, and high-speed I/O designs, has been selected from hundreds of nominations to be [...]
Read More

Chip-Package-Systems Convergence Workshop to be Held at DesignCon 2010

Key semiconductor and system design houses to share insights and practical solutions SAN JOSE, CALIFORNIA – January 26, 2009 – Apache Design Solutions, the technology leader in power and noise integrity for chip-package-systems (CPS) convergence, is sponsoring a workshop at DesignCon 2010 to facilitate industry-wide discussion on the challenges, methodologies, and techniques required for chip-package-systems (CPS) [...]
Read More

Apache Design Solutions to Participate at the Electronic Design and Solutions Fair 2010

Key Executive to present at the Low Power Design Session highlighting the latest solutions for low power designs SAN JOSE, CALIFORNIA – January 25, 2010– Apache Design Solutions, the technology leader in power and noise integrity for chip-package-systems (CPS) convergence, today announced that the company will be participating at the upcoming Electronic Design and Solution Fair [...]
Read More

Apache Design Solutions Closes 2009 with Record Quarter and Record Year

SAN JOSE, Calif. – January 21, 2010 – Apache Design Solutions, the technology leader in power and noise solutions for chip-package-systems (CPS) convergence, today announced that the company has achieved record bookings and revenue in Q4, while maintaining profitability. In addition, the company had double digit growth from 2008 to 2009 and became the market [...]
Read More

Practical Methodologies for Power / Signal Integrity of Chip-Package-Board Designs – A Industry Focused Workshop at DesignCon 2010

Is there a disconnect in your die, package and board design methodology? As technologies evolve to meet demands of higher performance, smaller size and lower cost, there are several challenges in the design of chips, packages and boards which must be addressed with an integrated analysis and verification methodology. For example, maintaining power integrity means ensuring [...]
Read More

Apache’s Power and Noise Solutions for Chip-Package-System Convergence Adopted by Sigma Designs for Digital Media SoCs

Contract reflects successful integration of Apache and Sequence Design, now delivering complete power and noise solutions from RTL to GDS SAN JOSE, CALIFORNIA – January 20, 2010 – Apache Design Solutions, the technology leader in power and noise solutions for chip-package-systems (CPS) convergence, today announced that Sigma Designs, Inc. (Nasdaq: SIGM), a leader in digital media [...]
Read More