Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an advanced, extremely fast timing engine to solve the complex timing issues associated with on chip variation (OCV) and multi-corner, multi-mode (MCMM) analysis.

Based on ATopTech’s Precision Optimization technology, Aprisa enables real design closure at smaller geometries through accurate timing correlation to industry sign-off tools. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process and avoid the exploding runtime issues associated with the variability in sub-micron designs.

“We have been pleased to work with ATopTech to qualify their digital implementation tools,” said S. T. Juang, senior director of Design Infrastructure Marketing at TSMC. “We look forward to continuing the collaboration to qualify Aprisa for the next technology node.”

“Aprisa has been successfully used by our customers in multiple 40nm design tapeouts,” said Dr. Ping-San Tzeng, ATopTech President and CTO. “Qualification by TSMC further confirms that our tools are production-ready for 40nm technologies, and gives customers even greater confidence that they can use Aprisa at this node and get excellent results.”

About ATopTech
ATopTech, Inc., is a technology leader in IC physical design. Its Precision Optimization technology offers real design closure at 65 nm and below. The company’s first product family, Aprisa, has extremely accurate correlation to golden sign-off tools, produces design rule check (DRC)-clean designs, features MCMM optimization at all phases, and offers 10-15 percent better timing and up to 10 percent less standard cell area than existing tools. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com

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Aprisa and Apogee are trademarks and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

One of the most convincing stories you can hear from any big EDA marketing person is that crosstalk is something which can only show up after the routes are laid down and thus needs to be fixed as a post-process step after routing. In theory, this looks reasonable since without real knowledge of the wires how can you predict coupling between them? But, if you step back and look at this from 1000 ft view, the same theory can apply to computing wire delays. Without routing how can you predict the wire delay and thus you need to route the design to accurately predict wire delays. But wait, how are we doing placement and placement-based optimization, CTS and post-clock optimization?

I recently surveyed few of my customers and P&R designers to check on how the big “three” handles SI in their flow:

Here is what I found/heard:

Company A : Detail Route the design. Fix all the regular timing. Turn on SI aware timing and do SI based timing optimization.

Company B : Route the design and later do SI based timing analysis and fix the regular and SI based timing. All this may be clubbed into one name but if you look at the logfile you can see the obvious!

Company C : They try to do some SI prevention during global routing based on heuristics and later some quick optimization following track assignment. Later post-detail routing, if you still have SI based timing violations left, you need to run post-route timing optimization.

The question anyone can have is what is wrong with the above approaches? These are perfectly valid approaches at 90nm or 130nm where SI was not significant in the designs. At 90nm, I know designers who’ll add 100ps extra margin to account for SI and not really do SI based timing analysis in implementation tool. They will just do it in sign-off tool and later run few ECOs to fix timing on outlier paths. There were several reasons for not doing SI based timing optimization in P&R tool:

a. P&R tool’s SI numbers wont correlate with sign-off tool’s SI prediction.
b. P&R tools runs really slow especially timer and extractor in post-route mode. So, if you want to do SI based timing optimization during post-route you are talking in days.
c. SI effects were not significant at 90 and 130nm. So, you can add extra margin and/or run few ECOs to close timing.

All this is changing at 65nm and 40nm. The crosstalk based timing effects are really significant. I have seen 500ps to 1ns difference in timing when between regular and crosstalk aware analysis. This is huge and cannot be solved by doing ECOs or adding 100ps or so margin.

So, all the designers who are working at 65nm and below are forced to run crosstalk aware timing closure flow in the P&R tool. The result be it company A, B or C, runtimes are loooong and no guarantee of complete SI based timing closure or correlation to sign-off tools (see my other post Myth # 9 : I need to tune R and C factors to get good correlation to sign-off tools and achieve predictable timing closure). While talking to one of my friend, I found that post-route SI aware timing optimization took 3.5 days in one tool and still it was not clean. Later, they did several (more than 10) ECOs for next 2 weeks to get timing closure!

This brings me back to my initial question: Crosstalk aware optimization is possible in post-route stage only? The answer is no. Any company, who wants you to believe otherwise are trying to hide the fundamental limitations with their P&R software to handle this effect appropriately.

Let me talk about how AtopTech’s Aprisa has tried to address this very issue. Instead of thinking about SI as a post-route issue, it is handled more in-line in the tool as any other thing like doing CTS or placement. Crosstalk prevention and fixing starts as soon as the global route is laid out. Here, actual optimization engine is called to optimize the design to fix and prevent crosstalk based timing effects. All this is not done based on some heuristics but actual timing windows etc. to accurately fix the problems where they will get reported by the sign-off tool. To do all this, P&R tool needs ultra-fast timer and extraction engines. Not only that, timer as well as extraction engines need to incremental to get to the next violating path faster. Both of this is achieved in Aprisa with help of multi-threaded extractor and timer. In addition, after doing global route and track assignment based SI fixing, the same is done during and after detail routing. Again, fast timer/extractor makes it possible to achieve timing closure in real time and not waiting for days to figure out if the design will be ultimately timing and routing clean.

In summary, if you are still struggling with timing closure on your chip, I will strongly recommend to challenge the methodologies setup for crosstalk aware timing closure…

Design teams need “golden” sign-off tools, from timing to back-end place-and-route and final verification. The intent is to ensure that final design and physical layout achieve the specified functional, timing and power requirements. Each of these tools produces its own analysis of the design and each has its own version of the data. Data integration and coordination across groups (and tools) always add time-consuming overhead. This invariably increases during final closure of the design, just at the point when it can be least afforded. As designs become more complex and as design teams become larger and more geographically dispersed, it is vital to have comprehensive information about the entire design in one place to enable better communication among the various teams.

The Tuscany Dashboard provides a Web interface that improves communication and visualization among design teams, and for management, enabling:

• Distributed development to close designs with challenging requirements even when engineers are working across multiple sites, with multiple chips in progress and with complex design constraints. Team members can share visualization and annotation to simultaneously optimize power, timing and placement.
• Access to consistent views of data collected from all tools in a heterogeneous physical design flow, including the status of metrics, visualization of critical paths and the history of the design.
• History of any modifications to the design database and the resulting changes to metrics, allowing comparisons from any point in the design timeline up to the state of the design today.

The Tuscany Dashboard works within all standard design flows, aggregating the output of the data from existing tools into a single source. The Tuscany Dashboard produces engineering views of current focal point issues or “hot spots” in the design. It also delivers customizable metrics, along with history and trends, and summarizes all in well-designed web pages.

“Tape-outs often go on and on without much ability to see whether progress is actually being made,” said Jim Hogan, private investor. “Each designer knows his or her own specific problems, but isn’t usually able to see the patterns of the whole. Tuscany Design’s approach definitely makes a lot of sense.”

“Most design teams have custom or unique tools added to fill specific gaps in the primary flow,” said Keith Mueller, president and CEO of Tuscany Design Automation. “This compounds the traditional communication gap that exists between front-end and back-end designers. The Tuscany Dashboard provides a solid platform for management tracking and ensures that designers can see what they need to see and do what they need to do to get to design closure.”

Tuscany Dashboard and Tego, Tuscany Design Automation’s structured design accelerator, are being demonstrated in Booth #3955 at the 46th Design Automation Conference in San Francisco from Monday, July 27th until Thursday, July 30th, 2009. Stop by to register for a chance to win a 32GB iPod Touch to help you visualize, manage, and control your music, much as Dashboard does for your design.

Pricing and Availability
The Tuscany Dashboard will be shipping to early beta customers on August 3, with production release scheduled for Q4. US pricing begins at $50,000 per license per year. For additional detail, please contact the Tuscany Design sales team at sales_staff@tuscanyda.com or call 1-408-868-4114.

About Tuscany Design Automation
Tuscany Design Automation develops and markets structured placement and visualization solutions for integrated circuit (IC) design that helps engineers achieve higher performance chips—such as microprocessors, graphics, DSP designs – at 65nm, 45nm, and below. The company’s technology provides web-enabled collaboration, access and implementation to the various groups and disciplines in the design team, helping them to better manage, optimize and reliably close designs. Tuscany Design also accelerates existing physical design flows by providing extensive visualization and rapid what-if analysis for CPU/DSP, cores, and other blocks using a structured design methodology. Tuscany Design is based in Fort Collins, Colorado, with offices in Silicon Valley. For additional information, see www.tuscanyda.com

Editorial Contact:
Cayenne Communication LLC
Michelle Clancy, +1-252-940-0981, michelle.clancy@cayennecom.com

As process nodes shrink, aggressive performance and power requirements become increasingly difficult to achieve. Tego’s structured design methodology puts a powerful new tool in the engineering arsenal, giving designers a high productivity alternative to full-custom design. Based on Badger, Tuscany Design’s high-performance platform, Tego includes an option for integrated timing and power analysis that allow engineers to quickly perform sophisticated what-if analysis on the design using intuitive graphical manipulation. Engineers using Tego develop intelligent, reusable, and durable physical structures, often realizing a surprising range of benefits:

• Deterministic design closure. With performance, power and area as primary objectives, another key value is that structured physical designs generally follow a systematic and predictable path to closure. Closure usually comes faster than by traditional techniques involving more trial-and-error.
• Optimal and balanced design metrics. Control, comprehensible physical designs and visibility to make tradeoffs enable simultaneous convergence on speed, power and area requirements.
• Reusable physical intellectual property (IP). Tego enables rapid porting of a structured physical design to other libraries or process nodes, giving designers not only reusable RTL IP but also highly differentiated and durable IP in the physical domain.

“Tego’s structured approach gives designers excellent control over physical design, enabling predictability within existing schedules and resource utilization,” said Dan Ellsworth, VP of Operations at Tuscany Design. “Customers have been able to achieve 25-40% improvement in power, maintaining or even improving performance, all without disrupting an existing design flow.”

Tego works with all standard place-and-route tools, creating a quick and seamless interface. From a gate-level netlist, the engineer is able to specify relative placement constraints and optimize placement of blocks. This placement is exported to existing physical design tools using a scripting-level interface. Tuscany Design customers are successfully using Tego with Cadence, IBM, Magma and Synopsys place-and-route flows.

“Structured methodologies in the past have largely been text- and command-driven,” said Volker Gierenz, senior engineer at Catena Radio Design. “That can make complex structures impractical, plus you’ve got long cycles to analyze what you’re doing. Tego visualizes a design, let’s you see incremental “what-ifs,” and provides analysis tools to optimize power, timing and area. Coming up on Tego was fast, and we have used it extensively in datapath-intensive design and module generation. I’ve been pleased with the results and the support.”

Tego has the advantage of either operating in the same data environment as Tuscany Dashboard, Tuscany Design’s solution to provide web-based collaboration and visualization of full-chip physical design data, or independently. Both are being demonstrated in Booth #3955 at the 46th Design Automation Conference in San Francisco from Monday, July 27th until Thursday, July 30th, 2009.

Pricing and Availability
Tego is in production now. US pricing begins at $120,000 per license year. For additional detail, please contact sales_staff@tuscanyda.com.

About Tuscany Design Automation
Tuscany Design Automation develops and markets structured placement and visualization solutions for integrated circuit (IC) design that helps engineers achieve higher performance chips—such as microprocessors, graphics, DSP designs – at 65nm, 45nm, and below. The company’s technology provides web-enabled collaboration, access and implementation to the various groups and disciplines in the design team, helping them to better manage, optimize and reliably close designs. Tuscany Design also accelerates existing physical design flows by providing extensive visualization and rapid what-if analysis for CPU/DSP, cores, and other blocks using a structured design methodology. Tuscany Design is based in Fort Collins, Colorado, with offices in Silicon Valley. For additional information, see www.tuscanyda.com

Editorial Contact:
Cayenne Communication LLC
Linda Marchant, +1-919-451-0776, linda.marchant@cayennecom.com

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