Apache’s Totem-SE Named a Finalist in EDN’S 20th Annual Innovations Awards Competition

SAN JOSE, Calif. – March 1, 2010 - Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced that Totem-SE, the industry’s first fully integrated power and noise analysis platform for analog, mixed-signal, memory, and high-speed I/O designs, has been selected from hundreds of nominations to be [...]
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Tanner EDA and Sound Design Technologies Announce Process Design Kit (PDK) Collaboration for Thin Film Technologies

SiPArray™ integrated passives technology combined with HiPer Silicon™ software provides breakthrough for complete A/MS IC design solution MONROVIA, California and BURLINGTON, Ontario, Canada — February 16, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs) and Sound Design Technologies (SDT), a leading designer and [...]
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Apache Design Solutions’ Power Analysis and Optimization Solutions Adopted by PLX Technology

RedHawk and PakSi-E deployed as the power analysis, sign-off, and optimization solutions for leading network storage designs SAN JOSE, CALIFORNIA – February 9, 2010 – Apache Design Solutions, the technology leader in power and noise integrity for chip-package-systems (CPS) convergence, today announced that PLX Technology, Inc. (NASDAQ: PLXT) has adopted Apache’s RedHawk-NX and PakSi-E solutions to [...]
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Tanner EDA to Exhibit at DesignCon: Software Solutions to Catalyze Innovation in Design, Layout and Verification of A/MS ICs

MONROVIA, Calif.. – January 26, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), will be exhibiting a complete line of software solutions for analog/ mixed-signal (A/MS) designers on February 2nd to 3rd in the Santa Clara Convention Center. What: Tanner EDA’s product suite, [...]
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Apache Design Solutions to Participate at the Electronic Design and Solutions Fair 2010

Key Executive to present at the Low Power Design Session highlighting the latest solutions for low power designs SAN JOSE, CALIFORNIA – January 25, 2010– Apache Design Solutions, the technology leader in power and noise integrity for chip-package-systems (CPS) convergence, today announced that the company will be participating at the upcoming Electronic Design and Solution Fair [...]
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Apache Design Solutions Closes 2009 with Record Quarter and Record Year

SAN JOSE, Calif. – January 21, 2010 – Apache Design Solutions, the technology leader in power and noise solutions for chip-package-systems (CPS) convergence, today announced that the company has achieved record bookings and revenue in Q4, while maintaining profitability. In addition, the company had double digit growth from 2008 to 2009 and became the market [...]
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ATopTech Introduces Industry’s First Top-Level Design Tool to Seamlessly Integrate All Hierarchical Functions with Block-Level Implementation

ATopTech, Inc., the primary technology leader in integrated circuit (IC) physical design solutions addressing the challenges of designing ICs at 65 nanometers and below, today announced the Apogee hierarchical physical design solution, which is the first in the industry to seamlessly integrate all the critical hierarchical design functions with a market-leading block-level implementation tool in a single environment.
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Oasys Design System Signs WorldWide OEM Agreement to Integrate Concept Engineering’s NlView Visualization Engine

Concept Engineering today announced that Oasys Design Systems, Inc., developer of the RealTime Designer full-chip physical register transfer-level (RTL) synthesis product, has signed a worldwide OEM license for Concept Engineering′s Nlview™ visualization engine
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TSMC Includes Azuro Vectorless Power Analysis and Multi-Corner CTS in Reference Flow 10.0

Azuro, Inc., a provider of software tools for semiconductor chip design, today announced that Taiwan Semiconductor Manufacturing Company (TSMC) has included Azuro’s PowerCentric™ multi-corner CTS and SASim™ vectorless power analysis as part of TSMC’s Reference Flow 10.0.
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