debugging
[Jack’s Paper Study Note] Managing Verification Error Traces with Bounded Model Debugging – Sean Safarpour et al. @ ASPDAC’10
http://www.eecg.utoronto.ca/~veneris/10aspdac.pdf Debugging is still the most time consuming part of IC design. Typical debug includes: (a) find out the checkers that indicate errors, (b) investigate waveforms of observation points (typically primary outputs) which may propagate errors to the checkers, (c) trace drivers of those observation points, (d) indicate error sources, (e) fix them, and finally [...]Read More
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