Debugging is still the most time consuming part of IC design. Typical debug includes: (a) find out the checkers that indicate errors, (b) investigate waveforms of observation points (typically primary outputs) which may propagate errors to the checkers, (c) trace drivers of those observation points, (d) indicate error sources, (e) fix them, and finally (f) re-run simulation to make sure the bugs disappear. The whole process is very, very labor intensive. Are there any automation tools that can help?

This paper presents the techniques for automatic debugging. Given design source code (RTL) and simulation error traces, the tool automatically tells designers “OK, the error sources come from those lines; please take care of them”. In other words, automatic debugging let designers skip steps (a)(b)(c)(d) and focus on steps (e)(f).

The basic underlying techniques of an automatic debugging tool are very similar to those of formal verification tools: BDDs, SAT, QBF, etc… Thus, the notorious challenges that accompany those techniques are the same – scaling – larger design with longer error traces. To conquer the problem, the authors introduce an important observation: “error sources are often excited temporally close to failure points”. They even make some experiments by simplifying the error behavior model and calculating the probability of error sources to prove the observation. No matter how realistic the experiment reveals, this part is the most interesting section that is worth reading again.

Based on the “error source temporal proximity to failure point” observation, the authors propose the approach “bounded model debugging” which is very similar to the concept of BMC (bounded model checking) used in formal property verification. The experiments show that 2.7 times more problems can be solved.

MONROVIA, California – March 2, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs) and IC Mask Design, an industry leader in the provision of physical design services to the global semiconductor industry, are collaborating on the development of a toolset to accelerate analog layout design. By exclusively licensing IC Mask Design’s patented layout acceleration technology and integrating it into Tanner EDA’s custom IC design suite, the partners will offer engineers an improved solution to boost layout productivity and quality.

Tanner EDA and IC Mask Design have been working together since 2007. In the course of working with customers to better understand their analog layout design challenges, the partners recognized a need to speed up the analog layout process. In Q2 2010 Tanner EDA will offer a breakthrough toolset based on IC Mask Design’s proprietary technology that accelerates and semi-automates physical design activities to improve productivity. The new tool will embed seamlessly into Tanner EDA’s powerful and robust layout editor. Designers will be able to automatically generate devices and structures that are silicon-aware and are contextually tuned for their own specific layouts. This new solution gives engineers and managers the benefits of quality and productivity by consistently applying analog layout knowledge and experience to eliminate errors and speed layout cycles.

Commenting on the collaboration, Greg Lebsack, president of Tanner EDA, said, “We are very focused on bringing innovations from trusted, well-regarded partners to our customers, and are pleased to be able to help them benefit from the depth and breadth of IC Mask Design’s experience in analog layout design. This collaboration is another instance of our desire to help analog designers develop breakthrough products with improved productivity and shorter design cycle times.”

Mr. Ciaran Whyte, co-founder and CTO of IC Mask Design, added, “We have always been impressed with the functionality and ease-of-use that Tanner EDA’s tools deliver to designers. It has been a natural extension of our working relationship to leverage our joint knowledge of analog layout challenges to further benefit analog layout productivity.”

Previews of the joint solution developed by Tanner EDA and IC Mask Design will be available from March 9th to March 12th in Booth #12 at the Design Automation & Test in Europe (DATE) conference in Dresden, Germany. The partners expect to ship this tool along with Tanner EDA’s next major product release – v15 of HiPer Silicon™ – at the beginning of Q2, 2010.

About IC Mask Design
Founded in 2002, IC Mask Design is a dynamic engineering organization and industry leader in the provision of Physical Design services to the global semiconductor industry. The company delivers services for analog, RF, mixed-signal and digital designs, and provides a range of training courses covering the complete spectrum of physical design.

About Tanner EDA
Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs). Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc. All other trademarks and trade names are the property of their respective owners.

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Totem-SE addresses the challenges associated with global coupling of power/ground noise, substrate noise, and package/PCB capacitive and inductive noise in analog and mixed-signal designs. It incorporates transistor-level noise injection, power/ground mesh and substrate network extraction, package/PCB modeling, dynamic analysis, and design debug in a single-flow environment. Delivering measurement-correlated accuracy and the capacity to handle standalone DRAM, Flash, and CMOS image sensors, Totem-SE enables designers to perform early stage prototyping, chip sign-off, and post-silicon debug.

”We are extremely pleased to once again be recognized by this prestigious award,” said Andrew Yang, CEO Apache Design Solutions. RedHawk, our flagship power integrity solution, was the winner in 2004 and Sentinel-CPM, the industry standard die modeling for Chip-Package-System, was the winner in 2008. This year’s nomination for Totem-SE demonstrates Apache’s commitment to continuously innovate and deliver solutions that meet the challenges faced by designers.”

During the months of February and March, EDN’s worldwide audience of electronics engineers and engineering managers will use an online ballot to select the ultimate winners from among the finalists. EDN’s editorial staff will also take part in determining the final winners. We encourage you to visit www.EDN.com/innovation20 to cast your vote for your favorite finalist. Winners will be announced at a reception and awards ceremony on April 26, 2010 in San Jose, CA.

About EDN and EDN.com
EDN serves the vital information needs of design engineers and engineering managers worldwide. EDN.com delivers a three-dimensional view of the electronics industry via news coverage, strategic business information, and in-depth technical content. (www.edn.com) EDN is published by Reed Business Information (www.reedbusiness.com/us), the largest business-to business publisher in the U.S. and a member of the Reed Elsevier Group plc (NYSE: RUK and ENL) – a world-leading publisher and information provider.

About Apache Design Solutions
Apache delivers the industry’s leading global power and noise analyses platform solutions for Chip-Package-System convergence. Apache’s innovative platforms address the unique power and noise challenges associated with specific design domains such as SoC (digital), analog / custom IP, and System (IC package, SiP, PCB) while providing a co-analysis environment that integrates the SoC and System worlds. From early-stage to sign-off, Apache’s products are adopted by 95% of the top 20 IDM, fabless semiconductor, and foundries for cost reduction, risk mitigation, and time-to-market improvements. Apache is a global company with over 200 employees and R&D centers and direct sales / support offices worldwide.

Apache Design Solutions, CMM, CPM, CoolTime, Columbus, NSPICE, RedHawk, PakSI-E, PsiWinder, PowerArtist, PowerTheater, Sahara, Sentinel, Totem, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc. All other trademarks mentioned herein are the property of their respective owners.

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WINSTON-SALEM, N.C. – February 16, 2010 - Triad Semiconductor, Inc., the industry’s leading supplier of via-configurable mixed-signal ASICs, today announced another first: the first ARM® Cortex™-M0 processor combined with high-resolution, high-precision analog resources: 16-bit ADC and 12-bit DAC and uncommitted op-amps. Triad’s TSX1001, implemented on the Mocha-1™ platform, provides the performance and low-power 32-bit processing of the ARM Cortex-M0 processor combined with high-precision analog features. Mocha-1 is based on Triad’s silicon-proven via-configurable array (VCA) technology, which allows embedded system designers to customize processor, analog, and digital features with lower power consumption and greater system cost savings than last-generation ASIC solutions.

The TSX1001 is a single-chip, mixed-signal processor that an embedded product developer can use to measure sensors and control actuators in products such as accelerometers, automatic meter readers, temperature sensors, capacitive touch inputs, touch screens, medical sensors and other devices requiring analog and processor resources integrated into small spaces using small, low-power batteries.

“We are seeing a general trend toward portable, low-power embedded processing, which requires 32-bit processing performance as well as a great deal of precision analog integration,” said Reid Wender, vice president of marketing at Triad Semiconductor. “The TSX1001 is ideal for many applications and, since the TSX1001 is built on Triad’s Mocha-1 configurable array, designers are able to quickly and inexpensively build working prototypes to verify functionality before committing to a new mixed-signal Cortex-M0 SoC solution optimized for a specific application.”

The TSX1001 will be supported by industry standard embedded software tool flows such as the ARM® RealView® development suite. Triad has released the TSX1001 design to fabrication; engineering samples will be available in May 2010.

About Triad Semiconductor, Inc.
Triad Semiconductor, Inc., a privately held fabless semiconductor company with headquarters in Winston-Salem, North Carolina, develops, prototypes and produces mixed-signal ASICs. The company’s groundbreaking via-configurable array (VCA) technology delivers ASICs with silicon-proven analog and digital functions more quickly and at lower cost than traditional full-custom approaches. Triad’s single-mask, via-only routing cuts engineering effort and fabrication time, resulting in fast-turn prototypes and allowing design changes to be made at minimal cost. For more information, please visit www.triadsemi.com or call (336) 774-2150.

Mocha is a trademark of Triad Semiconductor, Inc. All other product or service names are the property of their respective owners. All rights reserved.

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MONROVIA, California and BURLINGTON, Ontario, Canada — February 16, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs) and Sound Design Technologies (SDT), a leading designer and manufacturer of integrated passives and stacked-die assemblies, are collaborating to develop process design kits (PDKs) for analog/mixed-signal (A/MS) designers using Tanner EDA’s HiPer Silicon™ software. This collaboration gives Tanner EDA customers access to SDT’s innovative SiPArray™ integrated passives technology and SDT customers access to Tanner EDA’s A/MS tools for a complete IC design solution.

“Tanner EDA offers a perfect blend of productivity, price-performance and interoperability that is ideally suited to the needs of our analog/mixed-signal IC design customers,” stated Ian Roane, president and CEO of Sound Design Technologies. “Our collaboration with Tanner EDA provides our mutual customers with an advanced design platform and powerful design capabilities to integrate passive components into stacked die assemblies to reduce board space. This will enable them to capitalize on advanced 3D packaging capabilities for breakthroughs in miniaturization and high performance solutions.”

“Our collaboration with Sound Design Technologies is another example of enabling innovation by bringing leading-edge process and packaging capability to our customers,” commented Tanner EDA’s president, Greg Lebsack. “Our specialized IC design software combined with SDT’s integrated passives and chip-stacking technologies arm A/MS designers with breakthrough capabilities to simultaneously save space, improve quality and reduce power requirements.”

Availability of PDKs
Sound Design Technologies’ PDKs for Tanner Tools will be available in Q1 2010. For more information on PDK availability and access, please contact SDT’s Technology and Manufacturing services (techservices@sounddes.com) or John Zuk, vice president, marketing and strategic partnerships at Tanner EDA (john.zuk@tannereda.com).

About Tanner EDA
Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs). Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

About Sound Design Technologies
Sound Design Technologies Ltd., based in Burlington, Ontario, Canada, is a leading provider of miniature microelectronics manufacturing and packaging techniques as well as ultra-low power digital signal processors (DSP). Previously a division of Gennum Corporation, SDT has a 35-year history of innovation in the area, with a broad array of technologies such as 3D Chip Stacking and high density SiPArray(TM) - Thin Film high density Capacitor Arrays, adaptable for integrated passive device applications, to provide the right packaging solution for each customer’s unique needs. Originally developed for hearing aids, SDT’s products and technologies today are deployed in numerous markets and applications worldwide, including biomedical & industrial sensors, blood analyzers, LED/industrial lighting and wireless monitors. For more information on SDT products and services, visit www.sounddesigntechnologies.com. SDT is a portfolio company of Global Equity Capital, LLC, headquartered in Boulder, Colorado. For more information, visit www.globalequitycap.com.

HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc. Sound Design Technologies, Sound Design Technologies logo, SiPArray, thinSTAX are trademarks or registered trademarks of Sound Design Technologies, Ltd. All other trademarks and trade names are the property of their respective owners.
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SAN JOSE, CALIFORNIA – February 9, 2010 – Apache Design Solutions, the technology leader in power and noise integrity for chip-package-systems (CPS) convergence, today announced that PLX Technology, Inc. (NASDAQ: PLXT) has adopted Apache’s RedHawk-NX and PakSi-E solutions to improve their power grid design. PLX Technology is a leading global supplier of software-enriched silicon connectivity solutions for the enterprise PCI Express and consumer storage markets.

PLX chose RedHawk-NX and PakSi-E for their ability to provide accurate analysis of the power delivery network and to perform exploration of various design scenarios for optimal results. RedHawk-NX, the industry’s leading full-chip dynamic power sign-off solution, was able to identify the location of power weaknesses in the design. It also allowed PLX to determine optimal fixes, including package selection, pad placement location and pad sizing through its “what-if” analysis capabilities. PakSi-E, Apache’s IC package and system-in-package (SiP) 3D extraction and analysis tool, performs full package extraction and provides package parasitics for accurate SoC analysis.

“We need to constantly improve our power grid design and analysis methodology especially at 40nm and below with lower operating voltages,” said Vijay Meduri, vice president of engineering at PLX Technology. “Apache’s ability to handle the design size and complexity we anticipate will ensure us that our power network will meet the required specification and function properly.”

“PLX Technology’s semiconductor-based solutions are known for their high quality interoperability and performance,” said Craig Shirley, vice president of worldwide sales at Apache. “We are pleased to be able to help PLX with their power analysis and optimization, enabling them to mitigate risk and reduce cost.”

About Apache Design Solutions
Apache delivers the industry’s leading global power and noise analyses platform solutions for Chip-Package-System convergence. Apache’s innovative platforms address the unique power and noise challenges associated with specific design domains such as SoC (digital), analog / custom IP, and System (IC package, SiP, PCB), while providing a co-analysis environment that integrates the SoC and System worlds. From early-stage to sign-off, Apache’s products are adopted by 95% of the top 20 IDM, fabless semiconductor, and foundries for cost reduction, risk mitigation, and time-to-market improvements. Apache is a global company with over 200 employees and R&D centers and direct sales / support offices worldwide.

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Apache Design Solutions, CMM, CPM, CoolTime, Columbus, NSPICE, RedHawk, PakSI-E, PsiWinder, PowerArtist, PowerTheater, Sahara, Sentinel, Totem, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc. All other trademarks mentioned herein are the property of their respective owners.

LOUISVILLE, Colo. – Feb. 3, 2010 – The 47th Design Automation Conference (DAC), the premier conference devoted to electronic design and design automation (EDA), today announced that nominations for the Marie R. Pistilli Women in EDA Achievement Award are now being accepted. Nominations must be received no later than 5 PM, MST, Friday, March 5, 2010.

This annual award, named for Marie R. Pistilli, the former organizer of DAC, recognizes individuals who have helped to advance the profile of women in the EDA industry. This year’s honoree (to be announced prior to event) will be presented with the award during the Workshop for Women in Electronic Design (WWED) at DAC on Monday, June 14. The 47th DAC will take place from June 13-18, 2010, at the Anaheim Convention Center, Anaheim, CA. Registration for DAC and WWED will open in April.

“For 10 years the considerable contributions of women to the EDA industry have been recognized and honored through the Marie R. Pistilli Award,” said Pamela Parrish, chair of this year’s WWED committee. “We expect that this year’s nominees will continue to reflect the best and brightest EDA professionals, and we encourage people to nominate someone they know who has helped to advance the cause of women in EDA.”

The Marie R. Pistilli award is open to men and women in industry or academia with technical or non-technical backgrounds. Nominees are individuals who have made notable contributionsthrough work that has helped to advance the profile of women in the EDA industry. Past awardees have played key roles in launching or managing successful products that involved contributions from women, or created opportunities for women in the EDA industry. Others have been leaders within a company or organization who have helped raise the awareness of women, or mentors or role models for successful women in the EDA industry. Recent recipients of the award include:
45th DAC - Louise Trevillyan, IBM Research
44th DAC - Jan Willis, Calibra Consulting
43rd DAC - Ellen Yoffa, IBM Research
42nd DAC - Kathryn Kranen, Jasper Design Automation, Inc.
41st DAC - Mary Jane Irwin, Penn State Univ.
40th DAC - Karen Bartleson, Synopsys, Inc.
39th DAC - Ann Rincon, AMI Semiconductor
38th DAC - Deidre Hanford, Synopsys, Inc.
37th DAC - Penny Herscher, Cadence Design Systems, Inc.

For additional information on the award, including the nomination form, visit the DAC Web site at http://www.dac.com/47th/mrpaward.html.

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for Electronic Design Automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its Exhibition and Suite area with approximately 200 of the leading and emerging EDA, silicon, IP and design services providers. The conference is sponsored by the Association of Computing Machinery/Special Interest Group on Design Automation (ACM/SIGDA), the Electronic Design Automation Consortium (EDA Consortium), and the IEEE Council on Electronic Design Automation (CEDA).

Design Automation Conference acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
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One of the most challenging jobs of promoting any metric is actually not from the technical side. Instead, it is more likely from the political/business side. Big companies usually refuse to adopt proprietary methods, formats, or metrics to make sure they won’t be tethered to one single vendor. However, providing innovative solutions usually means having to use supplicated tools which only one or a few vendors can provide. This in turn usually means that the single vendor (or small group of vendors) will do their best to avoid competition. Therefore, a proprietary language or method will show up.

In the end, the proposed metric makes a lot of sense. The “proprietary” factor could make it difficult to go through the deployment process. This situation is worse between IP vendors compared to internal IP providers. Each IP vendor is an individual company. Trying to ask them to adopt some proprietary metric/tool together could be really tough.

The solution? Some people suggest that metric providers (aka startups) should create a fake company to work on the similar thing. In this way, the big companies won’t worry about being tied to one vendor Joking aside… No, we don’t know the answer yet but that’s the fun part of the game…

The semiconductor industry stands on the shoulders of its EDA tool providers and we must deliver the innovations and productivity necessary to feed and nurture the designers that have come to rely on us. It is only through this combination of innovation and productivity that we can provide the sustained value that will serve as the growth catalyst our broader ecosystem thrives on.

Innovation without context is irrelevant, however, so it’s essential that we deliver technology and capability in a manner that can be applied and exploited by the intended user. Through our interactions and discussions with designers, we consistently hear that many EDA design tools have exceeded the core requirements for a majority of the user base. In fact, just last week one of our customers referred to their usage of a “big three” vendor tool as “firing up the space shuttle to go to the corner store for milk.” This excess is understandable, as the market leaders are driven by the most extreme requirements for their (niche) user base working in the smallest geometries with unique needs. What’s tragic is that these cumbersome, overburdened tool flows have become the acceptable paradigm for the entire industry. The result is an ever-increasing gap between the requirements of most users and the features and functionality provided by the market-leading tools.

We believe 2010 is ripe for a new paradigm – one where “less is more.” An approach to tool design that delivers just the right mix of top-notch features and functionality that is squarely aligned with requirements. This concept of elegant, efficient design is what John Tanner embraced when he founded Tanner EDA twenty-two years ago and it’s an approach that we believe is not only relevant — but imperative — today.

Delivering on “less is more” is difficult. Anyone who has tried to distill a presentation to one slide or simplify a complex design knows that it requires more than just skill. One must achieve a deep level of understanding in order to get to the essence of the topic or issue. For EDA products, we think that functionality will not include superfluous features but instead will deliver excellent, tested and well supported solutions. This cannot be achieved in a vacuum; it requires the leveraging of users, partners, and even competitors. We believe this leverage – achieved through models such as “open innovation” (originally coined by Professor Henry Chesbrough) — is essential to achieving and sustaining “less is more.”

The open innovation business model offers a compelling framework for consideration in the EDA industry. With a core principle that ideas and intellectual capital can come from outside the traditional boundaries and connections, open innovation can bring new capabilities and technologies efficiently and effectively. Companies in the broader EDA ecosystem (such as Qualcomm) have already embraced open innovation as a means of effectively bolstering their innovation capacity and effectiveness.

While perhaps not considered a traditional example of open innovation, process design kits (PDKs) offer a congruent model for connecting technologies and intellectual property (IP) from one domain (IC fabrication) to another (design). One perspective on PDKs is that they are simply rule-sets that provide all users with a consistent base of information; effectively eroding opportunity for differentiation within a design. However, further consideration reveals that there are several other dimensions to PDKs where unique IP can be inserted for sustained differentiation.

One such dimension is PDK selection: simply identifying and applying technologies within and across foundries. A working example of this is Tanner’s recent collaboration with Sound Design Technologies (SDT). SDT and Tanner are launching a PDK to allow users to include advanced integrated passives technologies and 3D chip packaging capabilities in their designs. This offers the potential for substantial space savings as well as production and operating cost reductions. The other dimension here is access – where a tool vendor’s use of standard programming languages and opening of PDKs can provide a designer with the access and opportunity to customize and create differentiation.

Productivity is not exclusive from innovation; in fact, we believe that in this new era of doing more with less, designers will require more productivity from their EDA tools if they are to achieve the breakthroughs demanded by their customers. We believe that 2010 will see productivity requirements expand beyond the basics of performance, security and capability. Significant advances in the area of design environments and analog automation will achieve prominence. And designers will be able to use more efficient, focused tools to deliver profound breakthroughs for business and society.

What:
Exhibiting: The Mocha-1 array, which integrates an ARM® Cortex™-M0 ultra low power
32-bit processor running at 25MHz with 32Kbytes of EEPROM memory, 24Kbytes of SRAM, 75,000 gates of user configurable logic, and a wide selection of analog resources including op-amps, DACs, ADCs, resistors, capacitors, transistors and switches. Combining the Cortex-M0 with these configurable analog and digital resources allows Mocha-1 to realize a wide range of single-chip, mixed-signal SoC solutions for industrial, medical, sensor, Bluetooth low energy, and military/ aerospace applications. In Booth 827, Triad will be demonstrating a Bluetooth 4.0 (Bluetooth low energy) solution running on Triad’s Mocha FPGA emulation system allowing for rapid prototyping and development of complete Cortex-M0 solutions.

Presenting: “Via-configurable Analog ASIC: Technology and Applications,” a new alternative to full-custom analog/mixed signal ASICs that applies many of the concepts of deep-submicron digital structured arrays to larger geometry analog processes. Consequently a place-and-route tool (normally only for the digital domain) can be used to configure an analog ASIC while maintaining performance comparable to classical full-custom analog design. Specifically, this concept uses a single via layer to configure an entire device. These new devices are called via-configurable arrays (VCAs.) For additional information, please see http://www.designcon.com/2010/attendees/2_ta1/index.asp

Who:
Presenter: Jim Kemerling, Chief Technology Officer, Triad Semiconductor

When:
The presentation will take place on Tuesday, February 2, 2010 from 8:30am to 9:10am.
Exhibition hours are February 2nd and 3rd, 2010, from 12:30 to 6:30.

Where:
Santa Clara Convention Center, Santa Clara, CA.

About Triad Semiconductor, Inc.
Triad Semiconductor, Inc., a privately held fabless semiconductor company with headquarters in Winston-Salem, North Carolina, develops, prototypes and produces mixed-signal ASICs. The company’s groundbreaking via-configurable array (VCA) technology delivers ASICs with silicon-proven analog and digital functions more quickly and at lower cost than traditional full-custom approaches. Triad’s single-mask, via-only routing cuts engineering effort and fabrication time, resulting in fast-turn prototypes and allowing design changes to be made at minimal cost. For more information, please visit www.triadsemi.com or call (336) 774-2150.

Mocha and Mocha-1 are trademarks of Triad Semiconductor, Inc. All other product or service names are the property of their respective owners. All rights reserved.

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