FREMONT, Calif., July 29, 2010 – ClioSoft, Inc., developer of the premier hardware configuration management (HCM) system for the electronics design industry, has selected Advanced Semiconductor Technology Ltd. (AST) to be its exclusive distributor and technical representative in Israel. The agreement covers sales and support for ClioSoft’s SOS design data collaboration platform, which promotes collaboration and enables efficient management of hardware design data from concept to tape-out.

“Increasing demand for hardware configuration management in the Israeli electronics industry was the driver for this relationship,” said Srinath Anantharaman, founder and CEO of ClioSoft. “AST’s experience representing Synchronicity’s DesignSync family of products for the last nine years gives them unparalleled technical and market expertise in design data management and makes them the perfect partner for us.”

ClioSoft’s HCM products address the needs of large distributed enterprises by providing integrated data management within existing tool flows, easing management of hierarchically distributed designs and facilitating reuse of intellectual property. SOS works with data from any design flow, and is also seamlessly integrated with Cadence’s Virtuoso® AMS and Custom IC Design Platform, Synopsys’ Galaxy Custom Designer, Mentor’s ICstudio, and SpringSoft’s Laker™ Custom Layout Automation System.

“Although software configuration management is a given for most software teams, we are now seeing more and more demand for hardware configuration management,” said Gideon Amir, founder and CEO of AST. “ClioSoft has an excellent solution that is very easy to deploy for small teams and scales well to meet the demands of large multi-site design teams. We see a great opportunity for the SOS product line in Israel.”

About ClioSoft:

ClioSoft is the premier developer of hardware configuration management (HCM) solutions. The company’s SOS design data collaboration platform is built from the ground up to handle the requirements of hardware design flows. The SOS platform gives design teams the freedom and flexibility to choose the way they work, share and collaborate, enabling efficient management of design data from concept through tape-out and improving global team productivity. Custom engineered adaptors seamlessly integrate SOS with leading design flows – Cadence’s Virtuoso® AMS and Custom IC Design Platform, Synopsys’ Galaxy Custom Designer, Mentor’s ICstudio, and SpringSoft’s Laker™ Custom Layout Automation System. ClioSoft’s innovative Universal DM Adaptor technology “future proofs” data management needs by ensuring that data from any flow can be meaningfully managed.

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All trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Media Contact:

Linda Marchant, Cayenne Communication, 919-451-0776, linda.marchant@cayennecom.com

SANTA CLARA, CA, — July 27, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform), today announced that SiliconFile Technologies Inc., a leading fabless provider of CMOS image sensors, has selected the AFS Platform for complex-block verification of its image sensor ICs for mobile imaging applications.

“We spend a significant amount of effort on block-level verification of our CMOS image sensors,” said Do Yeong Lee, Chief Technology Officer at SiliconFile. “After extensive evaluation, we selected the Analog FastSPICE Platform for complex-block verification of our image sensors because it delivered nanometer SPICE accurate results 5x-10x faster than traditional SPICE simulators.”

The Analog FastSPICE Platform is the industry’s only unified circuit verification platform for analog, mixed-signal, and RF design. It always delivers nanometer SPICE accurate results, while providing 5x-20x higher performance than traditional SPICE, >10 million-element capacity, and the industry’s only comprehensive device noise analysis. The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. It includes licenses for AFS Nano SPICE simulation, AFS circuit simulation, AFS Co-Simulation, AFS Transient Noise Analysis, and AFS RF Analysis.

“We are very pleased that SiliconFile Technologies, a leading developer of CMOS image sensor ICs for mobile, videoconferencing, and surveillance applications, has selected the Analog FastSPICE Platform,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. “SiliconFile’s selection validates, once again, that Berkeley Design Automation is an essential partner to leading edge companies in the mobile imaging revolution.”

About Berkeley Design Automation

Berkeley Design Automation, Inc. (BDA) is the recognized leader in advanced analog, mixed-signal, and RF (AMS/RF) verification. The BDA Analog FastSPICE unified circuit verification platform (AFS Platform) combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Over seventy companies, including 15 of the world’s top 20 semiconductor companies, use the AFS Platform to efficiently verify AMS/RF circuits. Founded in 2003, the company has received several industry awards in recognition of its technology leadership and impact on the electronics industry. The company is privately held and backed by Woodside Fund, Bessemer Venture Partners, Panasonic Corporation, NTT Corporation, IT-Farm Corporation, and MUFJ Capital. For more information, visit http://www.berkeley-da.com.

Analog FastSPICE, AFS Nano, and WaveCrave are trademarks of Berkeley Design Automation, Inc. Berkeley Design and BDA are registered trademarks of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

PR for Berkeley Design Automation – Cayenne Communication LLC

Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com

MONROVIA, California – July 20, 2010 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), has hired seasoned electronic design automation (EDA) sales professional Richard (Rick) McColloch as an account manager. McColloch, who reports directly to Hamed Emami, Tanner EDA’s vice president of worldwide sales, will manage northern California and strategic accounts.

“Rick is a true ‘solutions’ account manager with a long history in technology and EDA companies,” said Emami. “As we move to version 15 of our flagship HiPer Silicon analog IC and MEMS design flow tool suite, we need to strengthen and expand an account management team already noted for its expertise. Rick’s experience and reputation make him an asset to the team as our customer base continues to grow.”

Rick McColloch has been working in high technology sales, account management and strategic alliances since 1984, when he joined Unisys (Sperry) Corp. He comes to Tanner EDA from a senior sales account management position at Magma Design Automation, where his worldwide accounts included National Semiconductor, IDT, SanDisk, and Rambus. Prior to Magma, Rick managed a group of strategic accounts for Synopsys Corp. for 11 years, increasing revenue and tool adoption as well as managing account plans and supervising support for accounts such as Toshiba, Fujitsu, AMCC, Intel, Sun, NXP, Broadcom, and STMicroelectronics.

“Tanner EDA tools provide a powerful, elegant solution to help analog and mixed-signal engineers with the complete flow, from schematic capture, circuit simulation, and waveform probing to physical layout and verification,” said McColloch. “Design engineers badly need tools that provide just the right mixture of features – no extraneous ‘maybe-nice-to-haves’— that get the job done quickly and well with a very low learning curve. I look forward to helping customers understand and benefit from the Tanner EDA approach to accelerating analog design.”

About Tanner EDA

Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc.

All other trademarks and trade names are the property of their respective owners.

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Note to Editors:

A photo of Rick McColloch is available upon request

Media Contact :

Linda Marchant, Cayenne Communication LLC — 919-451-0776 linda.marchant@cayennecom.com

SANTA CLARA, CA, — July 13, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform), today announced that Stephen Meier has joined the company as vice president of engineering. A recognized EDA technology and management leader, Meier will lead the company’s world-class engineering organization as it continues delivering breakthrough nanometer circuit verification capabilities.

“Steve brings exceptional management skills, broad technical expertise, and an outstanding track record of delivering high-quality world-class tools,” said Ravi Subramanian, president and CEO at Berkeley Design Automation. “We are delighted to have him join our team as we rapidly grow and continue to deliver breakthrough analog, RF, and mixed-signal verification capabilities.”

Meier joins Berkeley Design Automation after more than 15 years at Synopsys, Inc., where he was vice president of engineering. Meier led Synopsys’ global development team for IC Compiler—the industry’s most successful nanometer-generation physical implementation system. Previously at Synopsys he led key development efforts in design for manufacturing, low-power design, testbench development, formal verification, and logic synthesis. Meier started his career at Intel, where he managed custom physical design tool development. He holds an MSEE from UC Berkeley and graduated Summa Cum Laude with a BSEE from the University of Michigan. Meier also holds a patent in low power design.

“Nanometer circuit verification has become one of the key design challenges in the semiconductor industry,” said Meier. “I’m excited to be joining Berkeley Design Automation- the company that is leading the industry in this area with breakthrough technology and a strong customer base. I look forward to leading the engineering team in developing innovative solutions to our customer’s toughest challenges.”

Dr. Raj Raghuram, who has served as the company’s vice president of R&D for over 3 years, is now the company’s senior architect of circuit simulation. Dr. Raghuram led the development of the company’s Analog FastSPICE from a circuit simulator to a complete verification platform. In his new role, he will focus on next-generation circuit simulation architecture and advanced algorithm development.

About Berkeley Design Automation

Berkeley Design Automation, Inc. (BDA) is the recognized leader in advanced analog, mixed-signal, and RF (AMS/RF) verification. The BDA Analog FastSPICE unified circuit verification platform (AFS Platform) combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Over seventy companies, including 15 of the world’s top 20 semiconductor companies, use the AFS Platform to efficiently verify AMS/RF circuits. Founded in 2003, the company has received several industry awards in recognition of its technology leadership and impact on the electronics industry. The company is privately held and backed by Woodside Fund, Bessemer Venture Partners, Panasonic Corporation, NTT Corporation, IT-Farm Corporation, and MUFJ Capital. For more information, visit http://www.berkeley-da.com.

Analog FastSPICE is a trademark of Berkeley Design Automation, Inc. Berkeley Design and BDA are registered trademarks of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

PR for Berkeley Design Automation – Cayenne Communication LLC

Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com

AFS Delivers Nanometer SPICE Accuracy 5x-10x Faster for Complex Mixed-Signal ICs

SANTA CLARA, CA, — June 22, 2010— Berkeley Design Automation, Inc., provider of the Analog FastSPICE™ unified circuit verification platform (AFS Platform), today announced that Technology Leaders & Innovators (TLi), a leading fabless developer of display semiconductor products, has selected the AFS Platform for full-circuit verification and device noise analysis of its complex mixed-signal ICs for display applications.

“Our timing controllers and LCD drivers require full-circuit verification at the transistor-level and device noise analysis with nanometer SPICE accuracy,” said Dr. Soonwon Hong, Vice President of TLi. “We selected the AFS Platform because it delivers identical results as traditional SPICE 5x-10x faster without tuning and it provides nanometer SPICE accurate transient noise analysis of our complex mixed-signal designs.”

The Analog FastSPICE Platform is the industry’s only unified circuit verification platform for analog, mixed-signal, and RF design. It always delivers nanometer SPICE accurate results, while providing 5x-20x higher performance than traditional SPICE, >10 million-element capacity, and the industry’s only comprehensive device noise analysis. The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. It includes licenses for AFS Nano SPICE simulation, AFS circuit simulation, AFS Co-Simulation, AFS Transient Noise Analysis, and AFS RF Analysis.

“We are honored that TLi, a leading developer of display semiconductor products, has selected the Analog FastSPICE Platform for design verification and device noise analysis of their complex mixed-signal designs,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. “TLi’s selection of the AFS Platform further demonstrates the unique technology capabilities that Berkeley Design Automation brings to leading semiconductor design companies.”

About Berkeley Design Automation

Berkeley Design Automation, Inc. (BDA) is the recognized leader in advanced analog, mixed-signal, and RF (AMS/RF) verification. The BDA Analog FastSPICE unified circuit verification platform (AFS Platform) combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Over seventy companies, including 15 of the world’s top 20 semiconductor companies, use the AFS Platform to efficiently verify AMS/RF circuits. Founded in 2003, the company has received several industry awards in recognition of its technology leadership and impact on the electronics industry. The company is privately held and backed by Woodside Fund, Bessemer Venture Partners, Panasonic Corporation, NTT Corporation, IT-Farm Corporation, and MUFJ Capital. For more information, visit http://www.berkeley-da.com.

Analog FastSPICE, AFS Nano, and WaveCrave are trademarks of Berkeley Design Automation, Inc. Berkeley Design and BDA are registered trademarks of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

PR for Berkeley Design Automation – Cayenne Communication LLC

Michelle Clancy, 252-940-0981, michelle.clancy@cayennecom.com

I sat  in during the User Track session on Chip-Package-System power delivery network design optimization.

Sorin Dobre from Qualcomm presented how they use a comprehensive time and frequency domain methodology to design and validate their wireless chip-package-board designs.  He highlighted the complexities associated with  time domain analysis in which he includes the chip layout, package RLCK model and a fitted model for the PCB in a multi-domain analysis framework. He uses a multi-cycle resonance frequency aware VectorLess methodology to define the excitation model for his time domain analysis of this system. The current signature for the final excitation model generates high energy around the system resonance frequency stressing the chip-package-system PDN.

Davide Pandini from ST Microelectronics, Agrate, presented results on power supply noise and EMI analysis and how it can be mitigated for the chips his group designs for the automotive market. He presented in the second part of his talk the results on a case study highlighting static and dynamic voltage drop and EMI results. He illustrated how power noise from the chip propagates along the chip/package/board supply lines and radiates to the air. He highlighted a methodology of controlling the dynamic switching on the chip to control the on-die noise/drop and hence the EMI coupling.

Erhan Erglin from AMD presented a methodology of dynamic voltage drop analysis for their high performance designs targeting CPU/GPU/APU applications. He presented arguments on the need for dynamic voltage drop analysis and why inductance, both on the package and on the chip have to be included for their designs using advanced processes. As supply voltages reach threshold voltage levels, dynamic voltage drop analysis highlights areas of switching noise that can cause the chip to fail. Static IR which has been used historically is useful to find gross violations and typically show small drop (3-4% range) for their designs. But to include the package/die inductance and capacitance and the simultaneous switching current, he highlighted the need for dynamic voltage drop analysis. He presented findings showing that the inclusion of on-die inductance changes not only the peak voltage drop number, but also changes the voltage drop map.

Ricky Yong from Intel, Penang, Malaysia, presented results on power noise analysis on their MTCMOS (power gate)  designs including silicon correlation results. He focused on dynamic power noise analysis for mode transition for his power gated designs. He highlighted how they perform on-die voltage drop measurements using sense lines and showed close match between measurement and simulation results. He also presented simulation results for different power-on sequences and correlation to measurements (within 4%).

Kyung-Tae Do from Samsung presented a methodology for estimating statistical leakage and the library/modeling support needed to achieve that. He highlighted that present techniques are not applicable for large macros and that a new technique is needed. His proposed methodology uses a combination of library characterization using Monte-Carlo simulations and silicon measurement based tuning.

Souvik Mukherjee from TI, Dallas, showed results on a different but equally critical area of IO sub-system design and the impact of power ground noise on IO/memory interface timing. He mentioned that an ideal SSO/SSN analysis methodology needs to accurately trade off between accuracy and efficiency of modeling, extraction and simulation flows. He presented results using the Sentinel-SSO technology from Apache on how the PDN noise and signal cross-talk impact can be included for IO/memory interface timing analysis. He presented results using this technique and compared that to silicon measurement results for a 45nm SoC based wireless platform.

Again thanks to the various DAC committees and to all the folks who made DAC 2010 a very useful and productive show.  Headed back home now

SANTA CLARA, CA – June 14, 2010 – Azuro, Inc., the provider of advanced clock and timing optimization tools for digital chip design, today announced version 5.2 of PowerCentric™, the company’s industry-leading clock tree synthesis tool. This release deploys a proprietary new criticality-aware clustering algorithm to further reduce clock insertion delays by an average of 15% without any impact on clock power, area or skew. The product also includes full support for version 1.1 of the Common Power Format (CPF).

“As our customers migrate to 40nm and 28nm, achieving the lowest possible insertion delays is becoming critical to manage timing closure in the backend of the design flow,” said Paul Cunningham, CEO of Azuro. “But the key challenge is how to achieve these insertion delays without an unacceptable impact on power. Criticality-aware clustering uniquely blends buffering for speed with buffering for power to achieve an average of 15% reduction in clock insertion delays while at the same time maintaining our core value proposition of reduced clock power.”

CPF support in PowerCentric 5.2 follows on from the company’s announcement of its membership into the Cadence Connections program in March (see http://www.azuro.com/news/pr_2010_03_03.html). PowerCentric 5.2 is available now and is already in production use at several of Azuro’s largest customers.

About PowerCentric™

PowerCentric is a clock tree synthesis tool for digital standard cell-based chip designs. It reduces chip power by up to 20% and reduces clock area and insertion delay by up to 30%. The product also dramatically increases productivity on designs with complex re-convergent multi-mode clock networks.

About Azuro

Azuro is an electronic design automation company supplying software tools for use designing digital semiconductor chips. The company’s unique clock and timing optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held. For additional information, visit http://www.azuro.com/

Contact

Cayenne Communication – Linda Marchant, (919) 451-0776, linda.marchant@cayennecom.com

New release of Rubix™ delivers 15% increase in clock frequency and full support for CPF 1.1

SANTA CLARA, CA – June 14, 2010 – Azuro, Inc., the provider of advanced clock and timing optimization tools for digital chip design, today announced version 1.4 of Rubix™, the company’s industry-leading clock concurrent optimization tool. This release deploys extensive refinements to the product’s underlying timing-driven placement, logic sizing, and useful skew-based clock tree synthesis algorithms, resulting in an average 15% increase in clock frequencies beyond traditional skew-balanced flows, 5% higher than the previous version of Rubix. The product also includes full support for version 1.1 of the Common Power Format (CPF).

“Rubix continues to build momentum within our existing customer base and also through several new customer engagements,” said Paul Cunningham CEO of Azuro. “At 40 and 28nm, building clocks to deliver the best timing rather than to be skew balanced is becoming a must-have to meet schedules and manage power consumption. With this new release of Rubix we are seeing yet further improvements in our already significant clock speed gains, even on high performance CPUs and GPUs. These improvements typically come with impressive 10 to 30% reductions in leakage power as well.”

Clock concurrent optimization is a new approach to clock tree synthesis which builds useful skew-based clocks concurrently with performing logic gate sizing and placement. The key defining characteristic of clock concurrent optimization is that the timing picture being considered by all its underlying algorithms is a true “propagated clocks” view of timing based on real propagation of clock signals through the clock network. For more information on clock concurrent optimization, see the white paper at http://www.azuro.com/rubix/white-paper.html

CPF support in Rubix 1.4 follows on from the company’s announcement of its membership into the Cadence Connections program in March (see http://www.azuro.com/news/pr_2010_03_03.html ). Rubix 1.4 is available now and is already in production use at several of Azuro’s largest customers.

About Rubix™

Rubix is a unified placement, sizing, and useful skew-based clock tree synthesis tool for digital standard cell-based chip designs. It increases clock frequencies by up to 25%, reduces leakage power by up to 30%, and accelerates timing closure in the backend of the design flow by up to two months.

About Azuro

Azuro is an electronic design automation company supplying software tools for use designing digital semiconductor chips. The company’s unique clock and timing optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held. For additional information, visit http://www.azuro.com/

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Contact

Cayenne Communication – Linda Marchant, (919) 451-0776, linda.marchant@cayennecom.com

SAN JOSE, CALIFORNIA  - June 14, 2010 – Apache Design Solutions, the technology leader in power integrity, noise closure, and reliability sign-off for chip-package-systems (CPS), today announced that Advanced Micro Devices, Inc. (NYSE: AMD), the only company who delivers both x86 microprocessors and leading-edge 3D graphics, has chosen Apache as their global supplier of power supply noise and reliability sign-off products. Through close collaboration on analysis and optimization from RTL to silicon, Apache’s PowerArtist, RedHawk, and Totem help AMD efficiently addresses critical power and noise challenges arising from digital, analog, mixed-signal, and custom IP design and SoC integration.

AMD uses PowerArtist to perform RTL power analysis and reduction to make trade-offs between power, area, and performance early in the design process. RedHawk enables early stage prototyping and optimization of the power delivery network, as well as supply noise and electro-migration (EM) sign-off. Totem provides transistor-level analysis of full-custom IPs and model generation for hierarchical SoC verification. AMD also generates Chip Power Models (CPM™) to achieve chip-package power and noise closure.

“AMD is committed to delivering innovative products to our customers by leveraging best-in-class architecture, circuit, design automation, and manufacturing technologies,” said Jim Miller, Corporate Vice President, Design Engineering at Advanced Micro Devices.  “Our expanded relationship with Apache is critical to AMD’s success in the sub-32nm era through the breadth and depth of their product offering and domain expertise, as well as through the quality and responsiveness of their R&D and support teams.”

“As AMD enters their fifth decade of delivering innovative products, we are proud that they have selected Apache as a partner for power, noise and reliability analysis,” said Andrew Yang, CEO of Apache Design Solutions. “We look forward to working closely with AMD to address the next generation challenges in performance-per-watt, device form factor and system risk mitigation.”

About Apache Design Solutions

Apache delivers the industry’s leading power and noise analyses platform solutions for Chip-Package-System convergence from RTL to sign-off. Apache’s innovative platforms address the unique power and noise challenges associated with specific design domains such as SoC (digital), analog / custom IP, and System (IC package, SiP, PCB) while providing a co-analysis environment that integrates the SoC and system worlds. Apache’s products are adopted by 90% of the top 25 IDM, fabless semiconductor, and foundries for cost reduction, risk mitigation, and time-to-market improvements. Apache is a global company with over 200 employees and R&D centers and direct sales / support offices worldwide.

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Apache Design Solutions, CMM, CPM, CoolTime, Columbus, NSPICE, RedHawk, PakSI-E, PathFinder, PsiWinder, PowerArtist, PowerTheater, Sahara, Sentinel, Totem, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc. All other trademarks mentioned herein are the property of their respective owners.

Contacts:

Apache Design Solutions

Yukari Ohno, (408) 457-2000, yukari@apache-da.com

Worldwide licensing agreement gives Altos high-performance, high-capacity GUI for characterization process

FREIBURG, Germany – June 14, 2010 – Concept Engineering today announced that Altos Design Automation has signed a worldwide licensing agreement to integrate and use Concept Engineering’s Nlview™ visualization engine to power their new generation debug and process control graphical cockpit. Altos provides ultra-fast, fully-automated characterization technology for the creation of library views to address key nanometer challenges such as low power, timing, yield and process variation. Nlview, coupled with Concept Engineering’s T-engine™ option for automatic transistor-level schematic generation, will give Altos a high-performance, high-capacity GUI that provides very detailed visual feedback about critical circuit attributes discovered by the Altos characterization engine.

“Concept’s schematic visualization engine gives designers compelling visibility, improved control, and easier validation of the characterization process, especially for large macro blocks,” said Jim McCanny, CEO of Altos Design Automation.

By automatically generating easy-to-read transistor-level schematics and transistor-schematic fragments, Nlview and T-engine give design engineers quick and detailed feedback about and control over the cells and complex macro blocks that are running through the Altos characterization engine. Cross-probing between schematic diagrams and other design views makes it easy to understand and fine-tune characterization, and to more quickly locate and optimize important circuit attributes in cells and macros. In addition, the GUI allows comfortable monitoring and control of the ongoing characterization process.

“Automated characterization for cells, macro blocks and memory has become a critically important element of chip design,” said Gerhard Angst, CEO and president of Concept Engineering. “It gives us great pride to be working with the Altos Design Automation team to improve this area of design.”

Prototype software with the integrated Concept Engineering visualization engine will be shown at the Altos booth (#1367) at the 47^th Design Automation Conference (DAC) in Anaheim, CA from June 14^th to 16^th. Concept Engineering’s technology for automatic schematic generation, navigation, and visualization will be on exhibit in booth # 513 at DAC.

About Concept Engineering

Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative automatic schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company’s customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information, see http://www.concept.de.

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Editorial Contact:

Cayenne Communication LLC for Concept Engineering in North America:

Michelle Clancy, +1-252-940-0981, michelle.clancy@cayennecom.com