[Jack’s Paper Study Note] Managing Verification Error Traces with Bounded Model Debugging – Sean Safarpour et al. @ ASPDAC’10

http://www.eecg.utoronto.ca/~veneris/10aspdac.pdf Debugging is still the most time consuming part of IC design. Typical debug includes: (a) find out the checkers that indicate errors, (b) investigate waveforms of observation points (typically primary outputs) which may propagate errors to the checkers, (c) trace drivers of those observation points, (d) indicate error sources, (e) fix them, and finally (f) [...]
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More on metrics…

As mentioned in the previous post, having a set of metrics and tools to measure the quality of a given verification environment is really critical. The metric should not only measure the quality of the tests but also the capability to capture any abnormal behavior. Before sharing how people were trying to do this, we would like to share some practical experiences that might be encountered on the road.
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SoC Verification Challenges – Adopt Checker Quality Metric to Guard IP Quality

As pointed out in the previous post, a not-well-verified IP can be a major killer for any SoC project. SoC integrators basically don’t have the time or resources to debug individual problematic IPs. A bad IP can really delay a project, if not kill it. Having a robust IP signoff process is really critical and adopting [...]
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Chip Power Model for Co-design

The advancement of silicon technology and packaging, PCB technology does not happen in isolation. There is a great deal of interdependence between the IC and the interconnect world that drives technological innovation – for example, the rapid scaling of silicon and the need for high speed transmission is followed by higher performance, lower cost packages. [...]
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Verification Challenges — SoC

One of the major headaches when building a SoC is the quality of the adopted IP. A general SoC usually contains many IP cores which are either provided by the internal design team or purchased from 3rd party providers. An IP block usually comes with a complete function and performance spec for SoC integrators. However, [...]
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Power-Aware Debugging - the Languages

We have been working on the power-aware related projects for a while and there are some interesting experiences and thoughts that we would like to share in several blog posts. Hope you will enjoy it and please feel free to give us feedback. As we all know, low-power has become a more, if not [...]
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Welcome to Techguri’s Verification Blog!

If you're looking for in-depth discussion of Verification, you'll find it in this blog.
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