Myth # 8 : Crosstalk aware timing fixing can be done in post-route stage only.

One of the most convincing stories you can hear from any big EDA marketing person is that crosstalk is something which can only show up after the routes are laid down and thus needs to be fixed as a post-process step after routing.
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Myth #9: I need to tune R and C factors to get good correlation to sign-off tools and achieve predictable timing closure.

Lately, I have been hearing from a lot of customers using some of the big EDA place-and-route tools that they need to tune resistance and capacitance factors to achieve good timing correlation to sign-off tools for 65 and 40 nm designs. This started to make me wonder why is this needed.
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Useful Skew-Based Optimization

Clock trees are an integral part of any chip, and making them do what they should be doing is far less the expectation when designers try to build clock trees. Traditionally, clock trees are built to distribute clocks from the clock generator or clock port to the flip-flops or sink elements in the most efficient [...]
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