Hello

Welcome. My blog will mainly cover power-noise integrity and reliability validation for IPs and mixed signal designs. I will also be blogging on methodology development and industry leading practices that we at Apache have developed and proliferated to the IP design community. Keep watching for more.
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Hello everyone!

Hello everyone and welcome to my blog! I will use this space to share my experiences working here at Apache in bringing technologies that help our customers make their designs more likely to succeed the first time around and at the lowest unit cost looking at chip design holistically considering the package it goes in [...]
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Addressing Power noise challenges of today’s SOCs

Hello World! Welcome to my blog… Stayed tuned for postings on topics associated with power noise challenges of your SOC design and tips/tricks to address them
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Welcome to my nook!

Welcome to my blog – a place for us to share experiences and talk about applications that will help make better semiconductor chips and systems. In the coming months, I will talk about IC-Package-System co-design; about melding the different chip and system worlds to achieve true design, analysis and verification closure. I look forward to [...]
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IC/Package/SIP

The ultimate blogsite and information source for IC/Package/SIP...
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