I sat  in during the User Track session on Chip-Package-System power delivery network design optimization.

Sorin Dobre from Qualcomm presented how they use a comprehensive time and frequency domain methodology to design and validate their wireless chip-package-board designs.  He highlighted the complexities associated with  time domain analysis in which he includes the chip layout, package RLCK model and a fitted model for the PCB in a multi-domain analysis framework. He uses a multi-cycle resonance frequency aware VectorLess methodology to define the excitation model for his time domain analysis of this system. The current signature for the final excitation model generates high energy around the system resonance frequency stressing the chip-package-system PDN.

Davide Pandini from ST Microelectronics, Agrate, presented results on power supply noise and EMI analysis and how it can be mitigated for the chips his group designs for the automotive market. He presented in the second part of his talk the results on a case study highlighting static and dynamic voltage drop and EMI results. He illustrated how power noise from the chip propagates along the chip/package/board supply lines and radiates to the air. He highlighted a methodology of controlling the dynamic switching on the chip to control the on-die noise/drop and hence the EMI coupling.

Erhan Erglin from AMD presented a methodology of dynamic voltage drop analysis for their high performance designs targeting CPU/GPU/APU applications. He presented arguments on the need for dynamic voltage drop analysis and why inductance, both on the package and on the chip have to be included for their designs using advanced processes. As supply voltages reach threshold voltage levels, dynamic voltage drop analysis highlights areas of switching noise that can cause the chip to fail. Static IR which has been used historically is useful to find gross violations and typically show small drop (3-4% range) for their designs. But to include the package/die inductance and capacitance and the simultaneous switching current, he highlighted the need for dynamic voltage drop analysis. He presented findings showing that the inclusion of on-die inductance changes not only the peak voltage drop number, but also changes the voltage drop map.

Ricky Yong from Intel, Penang, Malaysia, presented results on power noise analysis on their MTCMOS (power gate)  designs including silicon correlation results. He focused on dynamic power noise analysis for mode transition for his power gated designs. He highlighted how they perform on-die voltage drop measurements using sense lines and showed close match between measurement and simulation results. He also presented simulation results for different power-on sequences and correlation to measurements (within 4%).

Kyung-Tae Do from Samsung presented a methodology for estimating statistical leakage and the library/modeling support needed to achieve that. He highlighted that present techniques are not applicable for large macros and that a new technique is needed. His proposed methodology uses a combination of library characterization using Monte-Carlo simulations and silicon measurement based tuning.

Souvik Mukherjee from TI, Dallas, showed results on a different but equally critical area of IO sub-system design and the impact of power ground noise on IO/memory interface timing. He mentioned that an ideal SSO/SSN analysis methodology needs to accurately trade off between accuracy and efficiency of modeling, extraction and simulation flows. He presented results using the Sentinel-SSO technology from Apache on how the PDN noise and signal cross-talk impact can be included for IO/memory interface timing analysis. He presented results using this technique and compared that to silicon measurement results for a 45nm SoC based wireless platform.

Again thanks to the various DAC committees and to all the folks who made DAC 2010 a very useful and productive show.  Headed back home now

For example, maintaining power integrity means ensuring that the entire power delivery from the voltage regulator on the PCB to the transistor on the die meets the device power supply requirement. This involves designing and optimizing the location of the voltage regulator, PCB and package de-coupling capacitors, power plane impedance, bump placement, on-die power grid, on-die de-coupling capacitors and switching transients in one design and analysis environment. Sufficient data sharing needs to happen between each of the design teams to ensure that the final working part delivers the supply current as needed by the chip within the specified voltage fluctuation limit.

On the other hand, high-speed memory and serial interfaces have very stringent requirements for simultaneous switching noise resulting from their need to maintain the fidelity of the transmitted and received signals. The simultaneous consideration of the IO ring design, IO and decoupling capacitor cell placement, input switching pattern, and package/board power and signal layouts is necessary to meet the goals of near end and far end SSN.

However, as these challenges become increasingly critical to the success of next generation of designs and systems, there is a singular lack of tools and methodologies to address these issues. Multiple disparate techniques exist with contention about the efficacy of each. Tool-sets exist but address only parts of the problem. For example, frequency domain analysis tools employing fast electromagnetic field solvers have looked at the mid and low frequency power delivery network system noise. Hence, time domain analysis tools are needed to solve for the high frequency noise that result from the switching of devices on the chip. But these time domain analysis tools need accurate models of the package and board to provide realistic on-die voltage and current waveform data. Similarly for IO signal integrity analysis, most analysis methods compromise either on the modeling sophistication or on data inclusiveness to generate results in a reasonable time-frame. For example, either the entire IO bank is not considered in the simulation or the signal/power ground network coupling are ignored. These trade-offs however impact the quality of the results which are critical in determining whether the chip-to-chip transmission will happen according to the specifications.

Apache is sponsoring a workshop at DesignCon where several industry experts from semiconductor and system design houses including Larry Smith from Altera, Jim Antonelis from Broadcom, Rick Brooks from Cisco, and Dr. Souvik Mukherjee from Texas Instruments are coming together to discuss their understanding of these challenges, to present the approaches they are taking and to outline the needs they have for tools and methodologies. Additionally, a panel discussion will be conducted to foster discussion on the techniques for chip model creation, package and board extraction tools and co-simulation methodologies. Perspectives on system modeling, extraction and simulation using EM tools, methods of accurate and distributed modeling of the IC and techniques of performing time domain and frequency domain simulations will be shared through presentations addressing both power and signal integrity issues. The topics will include practical methods for designing and evaluating the system performance. Another important topic is to define a method to build confidence in these methods. This workshop will be an open forum to share insights, discuss issues and present proven techniques. Such an open exchange of ideas and information from semiconductor and system companies will help to define the content of future technologies for chip and package modeling and system level verification of power and signal integrity.

I hope you will join us in the workshop “Practical methodologies for Power/Signal Integrity of Chip-Package-Board Designs” held from 9AM to noon on Thursday February 4th at the DesignCon conference in Santa Clara Convention center.

For more information on the workshop, please visit http://www.designcon.com/2010/attendees/th_th1/index.asp

You can also register for complimentary Exhibit PLUS pass to DesignCon for entry to the workshop. http://www.apache-da.com/apache-da/Home/NewsandEvents/Events.html

But what can of weaknesses are we talking about?
- The scan mode failure is one of the most unfortunate. As a known fact, with a static based analysis, the drop is purely proportional to the chip power consumption. Because of the slow frequencies of the scan chain(s), the average power gets smaller compared to the functional mode. But think dynamic!
In scan mode, you get most of your cells (FFs, Latches, clock buffers) switching at the same time – especially when there is only 1 single scan chain… This is the worst stressing switching scenario for your resistive PG grid and your inductive package.
Actually, since there is no way to get the PG grid designed to handle the test mode, we start to see more and more Apache users adjusting their test structures and strategies based on the corresponding dynamic analysis feedbacks.

- A second typical failure is when few set of standard cells, or even a single one, get isolated and weakly connected just because of the floorplan. The figure1 illustrates some cases.

figure1: Typical Floorplan

That’s what we use to call missing via, or impossibility to get vias as expected, at least in an automatic manner.

With a static approach, such a specific issue cannot be easily detected. A single standard cell does not consume enough average current to highlight such weakness in the static voltage drop map. But in dynamic mode, such weakness gets clearly identified.

Figure2: Supply Over TIme

Obviously, such weakness can be detected in dynamic if and only if the cell is switching during your simulation. So, even if, very luckily, you get a VCD file before your tapeout, you cannot guaranty this switching scenario will fire all those weakly connected standard cells… That’s exactly where the Apache’s Vectorless Approach will complete your analysis!
This very dedicated algorithm is automatically selecting the cells that will switch or not during your simulation. This selection is obviously dependant of the instances’ power, timing, logic, switching statistics, but it is also function of the topology of your design.  The tool identifies the weakly PG connected cells and makes them switch during your dynamic simulation. As a result, it gets very easy to viualize the consequences and quantify how bad could be the resulting dynamic voltage drop. Obviously, it is up to the designer to try different ‘what-if ‘ within RedHawk (add vias, straps or decap) in order to take the appropriate decisions,  but at least, he is aware of the weakness.

So, bottom line, if you want your chip first time right, don’t stay static and move for a dynamic solution!

Jerome

There are many aspects of chip-package-system co-analysis such as signal integrity, power integrity and electromagnetic interference. For now, let’s look at the system power integrity aspect of co-analysis. The noise on the power supply is becoming a major source of noise that can cause a rail collapse, and directly impact the noise margins and the timing. The power delivery network spans multiple domains, from the VRM and through the board and package to the IO regions of the dies and all the way to the transistors on the die. At present, due to the absence of a single analysis platform that can read in the chip layouts and the package/board layouts to perform power noise simulations in one unified run, a model based approach is in-vogue. In this method, there are key ingredients: (a) comprehensive model of the chip(s), (b) accurate model of the package and board, and (c) a co-simulation platform that can take these models appropriately to perform the required simulations (frequency domain, DC, or transient). The rest of this blog discusses the die model requirements (part a) and its application in a system level analysis.

The requirements for a die model must be understood to perform an accurate system level analysis. The die must be represented with the electrical and physical properties of the chip (wires, RDL, cell/IP/macro characteristics and placement etc) and must be a compact model that contains:

(1) Current consumption profiles over different parts of the chip in a spatial and temporal sense, for every domain and at every pin.  This current signature can reflect different operating modes of the chip and can be triggered through test patterns in the form of VCDs or by using a statistical vector generation engine such as Redhawk.

(2) Parasitics present on the chip to provide an effective Rdie and Cdie which is domain specific and reflects the layout and the technology of the chip.

Such a model can be used for chip-package-system (CPS) analysis and optimization during different stages of the design cycle. In the early stages of the chip when only the power grid prototype is available, the die model can contain only the parasitic components because the chip switching activity cannot be determined. Such a model is sufficient to perform a CPS frequency domain analysis to optimize the impedance and resonance frequency points. As the chip design progresses, the die model must incorporate incremental transient current information (for DC and transient analysis ) and become an accurate representation of the die that will ultimately correlate with measurement.

There are several aspects of the power delivery network design that must be optimized and verified, such as PCB stackup, VRM placement, de-coupling capacitance selection and placement, package layer, socket and connector selection, pin assignments and placement. The basic goal is to minimize the levels of noise and the impedance over a wide frequency range while limiting the cost, size, pin count, and number of layers. To accomplish this goal, a CPS co-analysis of the following types must be performed: (1) frequency domain (2) DC and (3) transient.

In the frequency domain, the die model is used in the combined package and board analysis to study the various resonance points and compute the impedance. The resonance frequency is estimated to ensure that it does not overlap with the functional frequency of the chip and its associated harmonics. The lower frequency range resonance points are determined mostly by the PCB and package elements. However, the resonance frequency at the higher frequency range (50+ MHz) is determined by the package/PCB inductance and the die capacitance.  The chip parasitic model as mentioned earlier needs to reflect all the various capacitances present in the chip (wires, gate, diffusion, well). It also needs to model the resistance (and inductance) of the power and ground routings and the channel resistances of the devices. Additionally, an accurate parasitic model of the die can determine whether the impedance is less than the target impedance.

For DC analysis, the current drawn at various parts of the die reflect either an average or a peak current situation. The system DC analysis will reflect the average drop at the die bump locations. For time-domain analysis the complexity of this modeling is higher due to several additional requirements: a) the model must provide current profile information for sufficiently long period of time to allow for meaningful CPS time-domain analysis capturing the LC resonance effects, b) the model must reflect various operating modes of the chips providing di/dt signatures in the transitions between such modes, and c) it must be spatially distributed over the chip to capture the placement of various circuits and their operations. Various studies have been done regarding “worst casing” the current signatures.

Historically design teams have explored ways to generate such die models. But these models have typically been unable to provide the accuracy or the modeling sophistication outlined earlier.  The Chip Power Model (CPM) technology from Apache pioneered the concept of a layout driven die modeling solution that met these needs. Essentially a CPM is generated subsequent to a die level RedHawk (for digital) or Totem (for custom/analog) power noise simulations. The information (layout, library, technology parameters) provided to either RedHawk or Totem is necessary and sufficient to generate a CPM with its accuracy commensurate with the detailed nature of the data provided. The generated chip power model is an electrical representation of the layout of the chip and its operating mode in an open Spice format that can then be connected to a package model.

Today, we cannot afford to work independent of each other. Design collaboration will lead to more innovation, improved quality and lower cost. Getting a good die model in the form of CPM is a first step towards a converged chip-package-system design methodology. Stay tuned for the next posts on package/board extraction and co-simulation technologies.

]]> http://www.techguri.com/2009/07/07/chip-power-model-for-co-design/feed/ 0 http://www.techguri.com/2009/07/06/mobility-chips-io-circuits-sip-designs-and-getting-ready-for-dac/ http://www.techguri.com/2009/07/06/mobility-chips-io-circuits-sip-designs-and-getting-ready-for-dac/#comments Mon, 06 Jul 2009 23:35:18 +0000 Aveek Sarkar http://www.techguri.com/?p=406 Hope everyone had a great July 4th weekend. We are now three weeks away from DAC and before we know it we will be at Moscone Center. As we get ready for the conference, I wanted to share some information.

We are fortunate to have three key customers present in our booth. Harpreet Anand from Broadcom’s Mobility Group will share his experiences on using RedHawk from early in his design process to sign-off for a 45nm design and how the step by step approach helped reduce the overall design risks. Ralf Schmitt from Rambus will share his experiences on bringing up and using Totem on high speed I/O interface designs. Louis Liu from TSMC will highlight the design challenges that are prompting a move towards a SiP/3D IC based designs.

Having worked with both Ralf and Harpreet on power noise and reliability for UltraSparc processors, I know that they bring considerable experience and expertise to the work they do and their presentations not only will provide a window into the flows and methodologies they use, but also give an opportunity to understand the challenges they see confront their specific focus areas. Louis’s presentation gives us an opportunity to participate in a discussion on the issues he sees both designers and foundries face in supporting advanced SiP/3D TSV based designs. The concerns and the challenges in this are seems to be part of the keynote to be delivered by Dr. Fu-Chieh Hsu (TSMC).

Additionally there are presentations in the DAC User Track sessions covering several application areas of Apache products. Bando-san from Kobe University will share his experiences on using Totem for substrate noise analysis and silicon correlation for the same. Davide Pandini from ST Microelectronics will share his experiences of using Sentinel Chip Power/Emission Model technology for near field and far field emission study for his designs.

This year at Apache we are focusing on four key areas:

• The capacity and usability features in RedHawk-NX, which is the Next Generation RedHawk engine incorporating the Mesh Pattern Recognition (MPR) and Hierarchical Dynamic (CMM) technologies. Additionally this version of RedHawk rolls out RedHawk Explorer (RHE), which for the first time provides automated design weakness and root cause identification capabilities for power noise simulations.

• The power noise and reliability analysis capabilities in Totem covering power grid design analysis, signal electromigration and substrate noise analysis. Totem comes with a highly interactive layout editor like GUI that overlays the analysis results on the layout and highlights design weaknesses automatically allowing users to fix their designs interactively before committing to the final layout.

• The full package and board extraction support in Sentinel-PI with true 3D full-wave accuracy, its ability to read one or more die models (CPM ~ chip power models) and its flexibility to perform frequency domain, time domain and DC analyses in one integrated simulation platform.

• Co-design strategies looking at power delivery, signal noise, EMI and thermal challenges associated with integrating one or more dies in complex package structures (SiP, 3D/TSV, etc). One key area is to assess the impact of IO power noise on signal transmission and jitter. The Sentinel-SSO solution provides the ability to simulate an entire IO bank (e.g. DDR3) incorporating both power noise and signal cross-talk impact to signal propagation.

Hope you can make it to DAC. Drop by and say hi if you are around.

  As a matter of fact, when a chip is ‘ON’, it is meant to do something, whatever the final application. Therefore, millions of standard cells (or millions of transistors) are driving signals in a very specific way. To drive those output signals, each cell needs energy: they consume current.
When the signal is static, the cell is consuming a leakage current, which is a state dependant constant value. But when the signal is switching, the cell will consume a certain amount of current over the time. This amount of current depends on 4 main factors: the slew (transition), the charge (load), the switching direction (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) of the net and the supply voltage of the cell itself. The bigger is the net and the more aggressive is the timing, the higher will be the corresponding peak of current.
  The figures below represent the current consumption profile of a cell during a switching output event. 

This current profile is obviously also dependent of the cell structure (complexity, size). In other words, each cell, such as each transistor, does have its own characteristics depending of the output signal.

Note:  It is important to notice that the frequency of the net does not directly change the value of the peak of current but rather the frequency of this peak. In other words, the frequency is impacting the “average” current consumption (better known as “average power”).

It is mandatory for a tool such as RedHawk to perfectly understand and use these current profiles in a way that mimics their physical operation (e.g. the current draw should depend on the supply voltage to that transistor) to compute an accurate Dynamic Voltage Drop.  Since the chip is not only made of standard cells but includes also memories, analog and full custom IPs, it implies a wide range a different current profiles for each element. So far we store all those profiles in APL (Apache Power Library) format. This is a spice based characterization; we may develop a bit more this subject later in this blog.

So, a cell needs current to drive a net – fine – but we may wonder why we hear more and more about switching noise with the last new technologies. As matter of fact, since we are shrinking a lot the geometries, the output loads and the cells get reduced, and therefore the corresponding switching peak of current. On the other hands, still due to this shrinking, we end up with much more transistors and cells per mm². In other words, the issue is not coming from individual current cell consumptions but from thousands of cells that are potentially switching at the same time in a very small area of your die. The density increases faster than the peak of current reduction. The real source of noise is clearly a simultaneous switching matter.

Even if today some technics such as gated clocks or skew and phase control tend to limit the simultaneous switching events, the transistor density gets so high, that we have to control the switching current and hence the switching noise very carefully. Additionnally, the tight design requirements on the chip, its package and its board make it more difficult to supply these high switching current requirements quickly enough. Thus, we see increasing needs for co-design solutions like Sentinel and RedHawk for designers working on advanced technology designs.

The many beautiful places our users live and work.

The most common question I get prior to visiting Israel is if it’s safe. I have never felt otherwise. I have walked in the ancient streets in Jaffa or gone running along the Promenade in Haifa late at night and never felt insecure or concerned. On the other hand, the visits are extremely fruitful not only in understanding how our many products are used but also from the insightful feedbacks I get from all the design teams we engage in. Our users in Israel, either from their work on some of the most advanced and complex designs or from their focus on having the most price competitive product, have adopted our power noise analysis solutions in comprehensive manner using them not only in the flow we recommend but also by adapting it to their specific needs by working closely with our local and world-wide application engineering and RnD teams.

While RedHawk™ use for the SoC or digital circuit analysis has been wide-spread since we started working with our customers there, the visit offered tantalizing insights into how our customers have obtained considerable value from using our Totem™ solution on their taped-out or ongoing designs. They have used it to validate the IPs they obtain from internal or external design teams to highlight issues that the traditional netlist based flows that the IP design teams use have missed. They have also been able to simulate entire designs or blocks that they had to earlier partition and simulate either in pieces or partially. They have also benefitted from Totem’s integrated simulation driven signal line electromigration analysis for their advanced sub-65nm designs.

Quite a few of our customers there have had co-design methodologies, but our CPM™ (Chip Power Modeling) and Sentinel-PI technologies have given them an accurate, usable and robust framework to perform their chip-package-board co-simulations and design changes. The use of CPM in a model based design environment (one in which models of the package, board and die are cascaded and simulated in a Spice simulator) tend to have complexities especially if the package model is in the S-parameter format or Broadband Spice models which do not reflect the physical nature of the CPM netlist. Discussions of model based simulation flows with our users in Israel tend to revolve around the parameters used to generate the CPM in a manner that makes it most suitable for a hook-up to such package models and the feedbacks from our customer in Israel have helped clarify some of those questions. Other discussions revolve around the various simulation scenarios that can be used to create a CPM to make the combined chip-package-board transient analysis representative of various operating modes of the system.

Interest in Sentinel-PI continues to build up given the benefits it provides. Sentinel-PI first imports the die model (CPM) along with the package and board layouts. It performs circuit level connection (die bump to package bump, package ball to board solder) and performs an integrated analysis (DC, AC, transient or EMI) within a single environment. Thus, users not only benefit from Sentinel-PI’s true 3D full-wave modeling accuracy but also from its proper handling of die to package to board connections resolving inaccuracies or ambiguities that arise in a cascaded model based approach. Due to their work on high speed, sensitive circuits or from a need to control the design margins and the costs across these disparate domains, our customers appreciate Sentinel-PI’s value proposition. Many of our users benchmark Sentinel-PI against HFSS taking small representative circuits while others have qualified it against measurements. Those results have increased their confidence in using Sentinel-PI to extract their entire package and board layouts with 3D full-wave accuracy (which they are unable to do in other available 3D full-wave extraction tools) and to leverage its unified simulation environment. Hence I look forward to my next visits there to get feedback on their experience on using Sentinel-PI.

On a separate note, I am very thankful to one of our users in Haifa, who introduced us to Pichoto, a fabulous find in Zikhron Ya’akov. I will recommend it to any of the readers who happen to visit Haifa and are looking for a place to have dinner of local favorites paired with fabulous local wines.

Till next time, cheers or as my colleagues in Israel would say, L’Chaim.