Practical Methodologies for Power / Signal Integrity of Chip-Package-Board Designs – A Industry Focused Workshop at DesignCon 2010

Is there a disconnect in your die, package and board design methodology? As technologies evolve to meet demands of higher performance, smaller size and lower cost, there are several challenges in the design of chips, packages and boards which must be addressed with an integrated analysis and verification methodology. For example, maintaining power integrity means ensuring [...]
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Don’t stay Static, be Dynamic!

As a Power Integrity Experts company, we are very often called to investigate some production chip failures. Most of the time it is due to few obvious design weaknesses easily identified within RedHawk. The trouble is, those weaknesses are not detectable with a static voltage drop analysis - just between us, if a so called [...]
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Apache at DAC!

If you missed Jerome Toublanc giving the exhibitor presentation today in North Hall on stop by the Apache booth #722 South Hall to talk with him on this subject and learn more about RedHawk, Totem and Sentinel.
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Apache at DAC!

If you missed Jerome Toublanc giving the exhibitor presentation today in North Hall on Derisking Power and Noise in our System stop by the Apache booth #722 South Hall to talk with him on this subject and learn more about RedHawk, Totem and Sentinel.
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Chip Power Model for Co-design

The advancement of silicon technology and packaging, PCB technology does not happen in isolation. There is a great deal of interdependence between the IC and the interconnect world that drives technological innovation – for example, the rapid scaling of silicon and the need for high speed transmission is followed by higher performance, lower cost packages. [...]
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Mobility chips, I/O circuits, SiP designs and getting ready for DAC.

Hope everyone had a great July 4th weekend. We are now three weeks away from DAC and before we know it we will be at Moscone Center. As we get ready for the conference, I wanted to share some information. We are fortunate to have three key customers present in our booth. Harpreet Anand from Broadcom’s [...]
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What’s that Noise?

  It is always good to start a story from the very beginning. At Apache, we are all about identifying and fixing “dynamic” voltage drop issues, and not only on the chip but also in package and board. However, before talking about Dynamic Voltage Drop it is important to understand its origins: the switching noise.     As a matter [...]
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Musings from a recent trip…

Last week I was visiting our customers in various locations in Israel. In many ways this trip was important. We had just announced Totem™, our full-chip transistor level power noise and reliability analysis solution which many of our users in Israel have been using for some time. We were seeing increased acceptance of our co-design [...]
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Bonjour Everyone!

Bienvenue to my blog. This place will deal with Noise: sources and consequences in your SoC. That’s a wide topic, so stay tuned for next postings!
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Hello

Welcome. My blog will mainly cover power-noise integrity and reliability validation for IPs and mixed signal designs. I will also be blogging on methodology development and industry leading practices that we at Apache have developed and proliferated to the IP design community. Keep watching for more.
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