MOUNTAIN VIEW, Calif. – August 27, 2009 – Synfora, Inc., the premier provider of algorithmic synthesis tools for integrated circuit and system designers of large, complex processing applications, today announced that it has purchased Esterel Studio™, a tool suite developed by Esterel EDA Technologies. Esterel Studio is based on the Esterel synchronous programming language in use for the design of control logic and bus systems by three of the top 10 semiconductor companies in system-on-chip (SoC) designs.

“Esterel Studio is complementary to the PICO algorithmic synthesis platform and was already part of an integrated flow used by several of our customers,” said Synfora CTO Vinod Kathail. “This step is a part of our long-term vision of providing integrated solutions for application accelerators and more control-oriented IP.”

Esterel Studio is primarily used to design control-intensive silicon intellectual property (IP) blocks and complex reactive systems such as control circuits, embedded systems, human-machine interface and communication protocols. Companies such as STMicroelectronics, Texas Instruments, NXP and Intel have used the Esterel programming language for more than 50 production designs.
Esterel Studio supports a complete flow from design to verification and supports textual or graphical design of large state machines with arbitrary embedded data path, animated simulation and debugging. Esterel studio is able to generate either HDL (Verilog, VHDL) code or C / SystemC models from the same source code, which ensures that the models used in virtual platforms for software validation agree with the final hardware design. Esterel Studio also supports formal verification of the produced results, a critical capability for complex control-oriented designs. In conjunction with the PICO platform, this will provide Synfora customers with an integrated design environment for the development of both control-intensive and algorithmic-intensive blocks.

About the Synfora PICO Platform
The PICO Algorithmic Synthesis Platform provides productivity gains by creating application accelerators from an untimed C algorithm at the highest level of abstraction. PICO yields quality of results (QoR) that is competitive with manual design by using a unique parallelizing compiler and multi-level hierarchical abstraction and IP reuse. It offers the highest possible level of abstraction for large designs and has been proven to provide huge productivity gains on the largest production designs, not just on small blocks.

About Synfora
Synfora, Inc. is the premier provider of algorithmic synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs. Synfora’s PICO algorithmic synthesis platform offers designers of large, complex subsystems productivity gains at the highest-level design abstraction and delivers high QoR. Synfora serves customers worldwide in the audio, video, imaging, wireless, and security segments of the integrated circuit (IC) design market. The company’s investors are ATA Ventures, Foundation Capital, U.S. Venture Partners, Wafra, and Xilinx. For the latest information on Synfora, please visit http://www.synfora.com.

We are fortunate to have three key customers present in our booth. Harpreet Anand from Broadcom’s Mobility Group will share his experiences on using RedHawk from early in his design process to sign-off for a 45nm design and how the step by step approach helped reduce the overall design risks. Ralf Schmitt from Rambus will share his experiences on bringing up and using Totem on high speed I/O interface designs. Louis Liu from TSMC will highlight the design challenges that are prompting a move towards a SiP/3D IC based designs.

Having worked with both Ralf and Harpreet on power noise and reliability for UltraSparc processors, I know that they bring considerable experience and expertise to the work they do and their presentations not only will provide a window into the flows and methodologies they use, but also give an opportunity to understand the challenges they see confront their specific focus areas. Louis’s presentation gives us an opportunity to participate in a discussion on the issues he sees both designers and foundries face in supporting advanced SiP/3D TSV based designs. The concerns and the challenges in this are seems to be part of the keynote to be delivered by Dr. Fu-Chieh Hsu (TSMC).

Additionally there are presentations in the DAC User Track sessions covering several application areas of Apache products. Bando-san from Kobe University will share his experiences on using Totem for substrate noise analysis and silicon correlation for the same. Davide Pandini from ST Microelectronics will share his experiences of using Sentinel Chip Power/Emission Model technology for near field and far field emission study for his designs.

This year at Apache we are focusing on four key areas:

• The capacity and usability features in RedHawk-NX, which is the Next Generation RedHawk engine incorporating the Mesh Pattern Recognition (MPR) and Hierarchical Dynamic (CMM) technologies. Additionally this version of RedHawk rolls out RedHawk Explorer (RHE), which for the first time provides automated design weakness and root cause identification capabilities for power noise simulations.

• The power noise and reliability analysis capabilities in Totem covering power grid design analysis, signal electromigration and substrate noise analysis. Totem comes with a highly interactive layout editor like GUI that overlays the analysis results on the layout and highlights design weaknesses automatically allowing users to fix their designs interactively before committing to the final layout.

• The full package and board extraction support in Sentinel-PI with true 3D full-wave accuracy, its ability to read one or more die models (CPM ~ chip power models) and its flexibility to perform frequency domain, time domain and DC analyses in one integrated simulation platform.

• Co-design strategies looking at power delivery, signal noise, EMI and thermal challenges associated with integrating one or more dies in complex package structures (SiP, 3D/TSV, etc). One key area is to assess the impact of IO power noise on signal transmission and jitter. The Sentinel-SSO solution provides the ability to simulate an entire IO bank (e.g. DDR3) incorporating both power noise and signal cross-talk impact to signal propagation.

Hope you can make it to DAC. Drop by and say hi if you are around.

The many beautiful places our users live and work.

The most common question I get prior to visiting Israel is if it’s safe. I have never felt otherwise. I have walked in the ancient streets in Jaffa or gone running along the Promenade in Haifa late at night and never felt insecure or concerned. On the other hand, the visits are extremely fruitful not only in understanding how our many products are used but also from the insightful feedbacks I get from all the design teams we engage in. Our users in Israel, either from their work on some of the most advanced and complex designs or from their focus on having the most price competitive product, have adopted our power noise analysis solutions in comprehensive manner using them not only in the flow we recommend but also by adapting it to their specific needs by working closely with our local and world-wide application engineering and RnD teams.

While RedHawk™ use for the SoC or digital circuit analysis has been wide-spread since we started working with our customers there, the visit offered tantalizing insights into how our customers have obtained considerable value from using our Totem™ solution on their taped-out or ongoing designs. They have used it to validate the IPs they obtain from internal or external design teams to highlight issues that the traditional netlist based flows that the IP design teams use have missed. They have also been able to simulate entire designs or blocks that they had to earlier partition and simulate either in pieces or partially. They have also benefitted from Totem’s integrated simulation driven signal line electromigration analysis for their advanced sub-65nm designs.

Quite a few of our customers there have had co-design methodologies, but our CPM™ (Chip Power Modeling) and Sentinel-PI technologies have given them an accurate, usable and robust framework to perform their chip-package-board co-simulations and design changes. The use of CPM in a model based design environment (one in which models of the package, board and die are cascaded and simulated in a Spice simulator) tend to have complexities especially if the package model is in the S-parameter format or Broadband Spice models which do not reflect the physical nature of the CPM netlist. Discussions of model based simulation flows with our users in Israel tend to revolve around the parameters used to generate the CPM in a manner that makes it most suitable for a hook-up to such package models and the feedbacks from our customer in Israel have helped clarify some of those questions. Other discussions revolve around the various simulation scenarios that can be used to create a CPM to make the combined chip-package-board transient analysis representative of various operating modes of the system.

Interest in Sentinel-PI continues to build up given the benefits it provides. Sentinel-PI first imports the die model (CPM) along with the package and board layouts. It performs circuit level connection (die bump to package bump, package ball to board solder) and performs an integrated analysis (DC, AC, transient or EMI) within a single environment. Thus, users not only benefit from Sentinel-PI’s true 3D full-wave modeling accuracy but also from its proper handling of die to package to board connections resolving inaccuracies or ambiguities that arise in a cascaded model based approach. Due to their work on high speed, sensitive circuits or from a need to control the design margins and the costs across these disparate domains, our customers appreciate Sentinel-PI’s value proposition. Many of our users benchmark Sentinel-PI against HFSS taking small representative circuits while others have qualified it against measurements. Those results have increased their confidence in using Sentinel-PI to extract their entire package and board layouts with 3D full-wave accuracy (which they are unable to do in other available 3D full-wave extraction tools) and to leverage its unified simulation environment. Hence I look forward to my next visits there to get feedback on their experience on using Sentinel-PI.

On a separate note, I am very thankful to one of our users in Haifa, who introduced us to Pichoto, a fabulous find in Zikhron Ya’akov. I will recommend it to any of the readers who happen to visit Haifa and are looking for a place to have dinner of local favorites paired with fabulous local wines.

Till next time, cheers or as my colleagues in Israel would say, L’Chaim.

Welcome. My blog will mainly cover power-noise integrity and reliability validation for IPs and mixed signal designs. I will also be blogging on methodology development and industry leading practices that we at Apache have developed and proliferated to the IP design community. Keep watching for more.

]]> http://www.techguri.com/2009/05/18/hello/feed/ http://www.techguri.com/2009/05/07/welcome-to-the-analog-design-blog/ http://www.techguri.com/2009/05/07/welcome-to-the-analog-design-blog/#comments Thu, 07 May 2009 17:11:01 +0000 TechGuri Administration http://www.techguri.com/?p=207 This is the first Analog Design post!