Synfora Acquires Esterel Studio™, Adds Control-Intensive IP Development Capabilities to Product Portfolio Complementary and Integrated Flow Already in Use by Top Tier Customers MOUNTAIN VIEW, Calif. – August 27, 2009 – Synfora, Inc., the premier provider of algorithmic synthesis tools for integrated circuit and system designers of large, complex processing applications, today announced that it has purchased [...]
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Apache at DAC!

If you missed Jerome Toublanc giving the exhibitor presentation today in North Hall on Derisking Power and Noise in our System stop by the Apache booth #722 South Hall to talk with him on this subject and learn more about RedHawk, Totem and Sentinel.
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Mobility chips, I/O circuits, SiP designs and getting ready for DAC.

Hope everyone had a great July 4th weekend. We are now three weeks away from DAC and before we know it we will be at Moscone Center. As we get ready for the conference, I wanted to share some information. We are fortunate to have three key customers present in our booth. Harpreet Anand from Broadcom’s [...]
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Musings from a recent trip…

Last week I was visiting our customers in various locations in Israel. In many ways this trip was important. We had just announced Totem™, our full-chip transistor level power noise and reliability analysis solution which many of our users in Israel have been using for some time. We were seeing increased acceptance of our co-design [...]
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Hello

Welcome. My blog will mainly cover power-noise integrity and reliability validation for IPs and mixed signal designs. I will also be blogging on methodology development and industry leading practices that we at Apache have developed and proliferated to the IP design community. Keep watching for more.
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Welcome to the Analog Design blog!

This is the first Analog Design post!
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