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	<title>TechGuri &#187; Concept Engineering</title>
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	<link>http://www.techguri.com</link>
	<description>Technical blog EDA, semiconductor industry</description>
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		<title>Concept Engineering’s NLVIEW Visualization Engine Adopted by Altos Design Automation to Power New Debug and Process Control GUI</title>
		<link>http://www.techguri.com/2010/06/15/concept-engineering%e2%80%99s-nlview-visualization-engine-adopted-by-altos-design-automation-to-power-new-debug-and-process-control-gui/</link>
		<comments>http://www.techguri.com/2010/06/15/concept-engineering%e2%80%99s-nlview-visualization-engine-adopted-by-altos-design-automation-to-power-new-debug-and-process-control-gui/#comments</comments>
		<pubDate>Tue, 15 Jun 2010 16:00:22 +0000</pubDate>
		<dc:creator>Concept Engineering</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[News]]></category>
		<category><![CDATA[Altos Design Automation]]></category>
		<category><![CDATA[Concept Engineering]]></category>
		<category><![CDATA[DAC 47]]></category>
		<category><![CDATA[high-capacity GUI]]></category>
		<category><![CDATA[Nlview]]></category>

		<guid isPermaLink="false">http://www.techguri.com/?p=1042</guid>
		<description><![CDATA[Worldwide licensing agreement gives Altos high-performance, high-capacity GUI for characterization process FREIBURG, Germany – June 14, 2010 – Concept Engineering today announced that Altos Design Automation has signed a worldwide licensing agreement to integrate and use Concept Engineering’s Nlview™ visualization engine to power their new generation debug and process control graphical cockpit. Altos provides ultra-fast, [...]]]></description>
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<h3><span><span><em>Worldwide licensing agreement gives Altos</em></span></span><span><span><em> high-performance, high-capacity<span> GUI for characterization process</span></em></span></span></h3>
<p><span><strong>FREIBURG, Germany – June 14, 2010</strong><span> – Concept Engineering today announced that </span></span><a href="http://www.altos-da.com/index.html"><span><span>Altos Design Automation</span></span></a><span><span> has signed a worldwide licensing agreement to integrate and use Concept Engineering’s </span></span><a href="http://www.concept.de/nlview.html"><span><span>Nlview™</span></span></a><span><span> visualization engine to power their new generation debug and process control graphical cockpit. Altos provides ultra-fast, fully-automated characterization technology for the creation of library views to address key nanometer challenges such as low power, timing, yield and process variation. Nlview, coupled with Concept Engineering’s</span></span><a href="http://www.concept.de/tengine.html"><span><span> T-engine</span></span></a><span><span>™ option for automatic transistor-level schematic generation, will give Altos a high-performance, high-capacity GUI that provides very<em> </em></span></span><span><span>detailed visual feedback about critical circuit attributes discovered by the Altos characterization engine.</span></span></p>
<p><span><span>&#8220;Concept&#8217;s schematic visualization engine gives designers compelling visibility, improved control, and easier validation of the characterization process, especially for large macro blocks,” said Jim McCanny, CEO of Altos Design Automation.</span></span></p>
<p><span><span>By automatically generating easy-to-read <span> </span>transistor-level schematics and transistor-schematic fragments, Nlview and T-engine give design engineers quick and detailed feedback about and control over the cells and complex macro blocks that are running through the Altos characterization engine. Cross-probing between schematic diagrams and other design views makes it easy to understand and fine-tune characterization, and to more quickly locate and optimize important circuit attributes in cells and macros. In addition, the GUI allows comfortable monitoring and control of the ongoing characterization process.</span></span></p>
<p><span><span>&#8220;Automated characterization for cells, macro blocks and memory has become a critically important element of chip design,&#8221; said Gerhard Angst, CEO and president of Concept Engineering. &#8220;It gives us great pride to be working with the Altos Design Automation team to improve this area of design.&#8221;</span></span></p>
<p><span><span>Prototype software with the integrated Concept Engineering visualization engine will be shown at the Altos booth (#1367) at the </span></span><a href="http://www2.dac.com/"><span><span>47<sup>th</sup> Design Automation Conference</span></span></a><span><span> (DAC) in Anaheim, CA from June 14<sup>th</sup> to 16<sup>th</sup>.<span> </span>Concept Engineering’s technology for automatic schematic generation, navigation, and visualization will be on exhibit in booth # 513 at DAC. </span></span></p>
<p><span><span><strong>About Concept Engineering</strong></span></span><span><span> </span></span></p>
<p><span><span>Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative automatic schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company&#8217;s customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information, see </span></span><a href="http://www.concept.de"><span><span>http://www.concept.de</span></span></a><span><span>. </span></span></p>
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<p class="MsoNormal"><span><strong>Editorial Contact:</strong></span><span><span></span></span></p>
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<p class="MsoNormal"><span>Cayenne Communication LLC for Concept Engineering in North America:</span></p>
<p class="MsoNormal"><span><span lang="FR">Michelle Clancy, +1-252-940-0981, </span></span><a href="mailto:michelle.clancy@cayennecom.com"><span><span lang="FR">michelle.clancy@cayennecom.com</span></span></a><span><span lang="FR"> </span></span></p>
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		<title>Concept Engineering Enhances Automatic Transistor-level Schematic Generation Technology</title>
		<link>http://www.techguri.com/2010/06/15/concept-engineering-enhances-automatic-transistor-level-schematic-generation-technology/</link>
		<comments>http://www.techguri.com/2010/06/15/concept-engineering-enhances-automatic-transistor-level-schematic-generation-technology/#comments</comments>
		<pubDate>Tue, 15 Jun 2010 15:57:33 +0000</pubDate>
		<dc:creator>Concept Engineering</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[News]]></category>
		<category><![CDATA[A/MS circuits]]></category>
		<category><![CDATA[analog]]></category>
		<category><![CDATA[Concept Engineering]]></category>
		<category><![CDATA[DAC 47]]></category>
		<category><![CDATA[digital circuits]]></category>
		<category><![CDATA[SoCs]]></category>
		<category><![CDATA[SpiceVision PRO]]></category>
		<category><![CDATA[T-engine]]></category>

		<guid isPermaLink="false">http://www.techguri.com/?p=1040</guid>
		<description><![CDATA[Improves analog and mixed- signal visualization capability for T-engine™ and SpiceVision PRO ® FREIBURG, Germany – June 14, 2010 – With more analog building blocks being integrated into modern mixed-signal systems-on-chip (SoCs) and with parasitic effects getting more complex with each process node, there is clear and increasing need for improved mixed-mode, analog, and parasitic [...]]]></description>
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<h3><em><span> </span>Improves analog and mixed- signal visualization capability for T-engine™ and SpiceVision PRO ®</em></h3>
<h3>FREIBURG, Germany – June 14, 2010<span style="font-weight: normal;"> – With more analog building blocks being integrated into modern mixed-signal systems-on-chip (SoCs) and with parasitic effects getting more complex with each process node, there is clear and increasing need for improved mixed-mode, analog, and parasitic network visualization capabilities. Recognizing this need, Concept Engineering has significantly improved analog and mixed-signal (A/MS) visualization capabilities for </span><a href="http://www.concept.de/tengine.html"><span style="font-weight: normal;">T-engine</span></a><span style="font-weight: normal;">™, the company’s core technology for automatic transistor-level schematic generation. The enhanced T-engine automatically draws easy-to-read and easy-to-understand schematics for both A/MS and digital circuits.</span></h3>
<h3><span style="font-weight: normal;">T-engine creates schematic drawings or schematic fragment drawings for device-level information as usually defined in SPICE netlists and SPICE model descriptions. Working at the device level, design engineers get very detailed visual feedback about the problems they have to solve and can more easily optimize their designs, intellectual property (IP) blocks or library cells for low power, yield, or signal integrity. </span></h3>
<h3><span style="font-weight: normal;">T-Engine is integrated into Concept’s </span><a href="http://www.concept.de/sv_index.html"><span style="font-weight: normal;">SpiceVision PRO</span></a><span style="font-weight: normal;">®, the company’s transistor-level debugging tool. Designers of electronic integrated circuits (ICs) and SoCs use SpiceVision PRO to visualize critical information such as circuit structure, device interaction and parasitic elements, at the transistor level, so that they can more easily and accurately understand and tune designs for maximum performance, lower power consumption or reliability.</span></h3>
<h3><span style="font-weight: normal;">Original equipment manufacturer (OEM) customers use T-engine to quickly realize debugging cockpits for their electronic design automation (EDA) tools at a very competitive cost and with very high quality. T-engine’s easy customization gives OEMs a high-performance, high-capacity graphical user interface (GUI) that fits into customers’ applications while allowing the OEM to concentrate on product core features. </span></h3>
<h3><span style="font-weight: normal;">“Concept Engineering has a long history of providing its OEM customers with leading visualization technology for all design levels, including system-level, RTL-level, gate-level and transistor-level,” said Gerhard Angst, CEO and president of Concept Engineering. “With the addition of enhanced analog and mixed-signal visualization, we are bringing even more visibility into problems that designers face today.”</span></h3>
<h3><span style="font-weight: normal;">The latest T-engine and SpiceVision PRO software will be demonstrated in the Concept Engineering booth (#513) at the </span><a href="http://www2.dac.com/"><span style="font-weight: normal;">47</span><sup><span style="font-weight: normal;">th</span></sup><span style="font-weight: normal;"> Design Automation Conference</span></a><span style="font-weight: normal;"> (DAC) in Anaheim, CA from June 14</span><sup><span style="font-weight: normal;">th</span></sup><span style="font-weight: normal;"> to 16</span><sup><span style="font-weight: normal;">th</span></sup><span style="font-weight: normal;">. </span><a href="http://www.altos-da.com/index.html"><span style="font-weight: normal;">Altos Design Automation</span></a><span style="font-weight: normal;"> also will be showing prototype software with integrated T-engine capability in booth #1367. </span></h3>
<p><strong>About Concept Engineering</strong></p>
<p>Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company&#8217;s customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information, see <a href="http://www.concept.de">http://www.concept.de</a>.</p>
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<p class="MsoNormal"><strong>Editorial Contact:</strong></p>
<p class="MsoNormal">Cayenne Communication LLC for Concept Engineering in North America:</p>
<p class="MsoNormal"><span lang="FR">Michelle Clancy, +1-252-940-0981, </span><a href="mailto:michelle.clancy@cayennecom.com"><span lang="FR">michelle.clancy@cayennecom.com</span></a><span lang="FR"> </span></p>
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		<title>Oasys Design System Signs WorldWide OEM Agreement to Integrate Concept Engineering’s NlView Visualization Engine</title>
		<link>http://www.techguri.com/2009/07/27/oasys-design-system-signs-worldwide-oem-agreement-to-integrate-concept-engineering%e2%80%99s-nlview-visualization-engine/</link>
		<comments>http://www.techguri.com/2009/07/27/oasys-design-system-signs-worldwide-oem-agreement-to-integrate-concept-engineering%e2%80%99s-nlview-visualization-engine/#comments</comments>
		<pubDate>Mon, 27 Jul 2009 16:28:46 +0000</pubDate>
		<dc:creator>Concept Engineering</dc:creator>
				<category><![CDATA[News]]></category>
		<category><![CDATA[Concept Engineering]]></category>
		<category><![CDATA[debugging GUI]]></category>
		<category><![CDATA[IC]]></category>
		<category><![CDATA[Inc.]]></category>
		<category><![CDATA[integrated circuits]]></category>
		<category><![CDATA[Nlview]]></category>
		<category><![CDATA[Oasys Design Systems]]></category>
		<category><![CDATA[physical synthesis process]]></category>
		<category><![CDATA[Plug-and-play integration]]></category>
		<category><![CDATA[RealTime Designer]]></category>
		<category><![CDATA[RTL code]]></category>
		<category><![CDATA[SoCs]]></category>
		<category><![CDATA[systems-on-chip]]></category>

		<guid isPermaLink="false">http://www.techguri.com/?p=474</guid>
		<description><![CDATA[Concept Engineering today announced that Oasys Design Systems, Inc., developer of the RealTime Designer full-chip physical register transfer-level (RTL) synthesis product, has signed a worldwide OEM license for Concept Engineering′s Nlview™ visualization engine]]></description>
			<content:encoded><![CDATA[<p><em>RealTime Designer, full chip physical synthesis tool now offers users a high performance and high capacity debugging cockpit</em></p>
<p><strong>FREIBURG, Germany – July 27, 2009</strong> – Concept Engineering today announced that Oasys Design Systems, Inc., developer of the RealTime Designer full-chip physical register transfer-level (RTL) synthesis product, has signed a worldwide OEM license for Concept Engineering′s Nlview™ visualization engine. Nlview is integrated into RealTime Designer to power its debugging GUI. Design engineers using RealTime Designer bundled with Nlview benefit from a high-performance, high-capacity debugging cockpit and from very detailed visual feedback about the RTL code and the physical synthesis process. </p>
<p>By automatically generating easy-to-read schematic diagrams from RTL code and RTL code fragments, Nlview gives design engineers quick and detailed feedback about the RTL design running through the Oasys physical synthesis process. Cross-probing between schematic and other design views makes it easy to understand and fine-tune the physical synthesis process. The Nlview engine helps designers of electronic integrated circuits (ICs) and systems-on-chip (SoCs) to visualize such critical information as circuit structure, critical path circuit fragments, parasitic components, device properties and signal values, so that they can more easily and accurately tune designs for low power or for maximum performance and more quickly locate and correct errors in their designs.  </p>
<p>“Run time and tool quality are attributes that are extremely important within our RealTime Designer product,” said Paul van Besouw, president and CEO of Oasys. “We selected Concept Engineering&#8217;s visualization engine because the product provided extreme performance with very high quality.”</p>
<p>RealTime Designer provides a new platform for nanometer design, delivering 10x to 60x runtime improvements over existing physical synthesis tools. A scalable tool that delivers quality results, RealTime Designer dramatically reduces place and route run times. Plug-and-play integration with existing EDA flows allows day-one usability. </p>
<p>“RealTime Designer is an exciting new tool for engineers working on full chip physical design” said Gerhard Angst, president and CEO of Concept Engineering. &#8220;We are very proud that Oasys has selected our visualization technology for their new full-chip physical synthesis product and that we are able to help OASYS to accelerate the design process for complex physical design implementation” </p>
<p>RealTime Designer bundled with the Nlview engine is available now. Product demonstrations can be seen at the Oasys booth # 3061 at the Design Automation Conference in San Francisco at Moscone Center from July 27 to July 30, 2009.  </p>
<p>Concept Engineering will also be showcasing their suite of products in Booth #918 at the Design Automation Conference.</p>
<p><strong>About Oasys Design Systems</strong><br />
Oasys Design Systems is a privately funded company providing Chip Synthesis technology, a fundamental shift in how synthesis is applied to the design and implementation of IC’s larger than 20 million gates. The company has attracted the support of legendary EDA leadership and its products are in use at leading edge semiconductor and systems companies worldwide. For more information visit the website at <a href="http://www.oasys-ds.com">http://www.oasys-ds.com</a></p>
<p><strong>About Concept Engineering </strong><br />
Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company&#8217;s customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. For more information, see <a href="http://www.concept.de">http://www.concept.de</a>. </p>
<p><strong><br />
Editorial Contact:</strong><br />
Cayenne Communication LLC for Concept Engineering in North America:<br />
Michelle Clancy, +1-252-940-0981, <a href="mailto:michelle.clancy@cayennecom.com ">michelle.clancy@cayennecom.com </a></p>
<p>Oasys Design Systems:<br />
Sanjiv Kaul, (408) 855 &#8211; 8531</p>
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