
Santa Clara, CA – January 19, 2010 — ATopTech, Inc., the primary technology leader in integrated circuit (IC) physical design solutions addressing the challenges of designing ICs at 65 nanometers and below, today announced that Aprisa, the company’s award-winning physical design solution, has been qualified for TSMC’s 40nm technology node, meeting the foundry’s requirements of [...]
Santa Clara, CA – January 11, 2010 — ATopTech, Inc., the technology leader in integrated circuit (IC) physical design solutions addressing the challenges of designing ICs at 65 nanometers and below, has appointed Jue-Hsien Chern as CEO. ATopTech also achieved profitability based on record sales from new customer adoption of Aprisa, the complete netlist to [...]
ATopTech, Inc., the primary technology leader in integrated circuit (IC) physical design solutions addressing the challenges of designing ICs at 65 nanometers and below, today announced the Apogee hierarchical physical design solution, which is the first in the industry to seamlessly integrate all the critical hierarchical design functions with a market-leading block-level implementation tool in a single environment.