Alpesh Kothari


Namaste! In this avatar I go by the name of Alpesh Kothari, Atoptech. My latest stint with this company is over 1.5 man-years before which I worked for 56 dog-years (1 man-year = 7 dog-years) at a big EDA company. I have spent my entire adult-hood working in EDA industry specifically in Place & Route arena. Don't get me wrong, I am still young!!!
Apart from supporting customers, solving their tools issues and helping them tape-out chips, I am also a full-time dad of two boys who are more demanding than my customers!
Alpesh Kothari has written 3 posts for TechGuri
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Myth # 8 : Crosstalk aware timing fixing can be done in post-route stage only.

By Alpesh Kothari ⋅ September 8, 2009 ⋅ Post a comment

One of the most convincing stories you can hear from any big EDA marketing person is that crosstalk is something which can only show up after the routes are laid down and thus needs to be fixed as a post-process step after routing.

Myth #9: I need to tune R and C factors to get good correlation to sign-off tools and achieve predictable timing closure.

By Alpesh Kothari ⋅ June 17, 2009 ⋅ Post a comment

Lately, I have been hearing from a lot of customers using some of the big EDA place-and-route tools that they need to tune resistance and capacitance factors to achieve good timing correlation to sign-off tools for 65 and 40 nm designs. This started to make me wonder why is this needed.

Useful Skew-Based Optimization

By Alpesh Kothari ⋅ May 28, 2009 ⋅ One comment

Clock trees are an integral part of any chip, and making them do what they should be doing is far less the expectation when designers try to build clock trees. Traditionally, clock trees are built to distribute clocks from the clock generator or clock port to the flip-flops or sink elements in the most efficient [...]