Chia-Chih Yen
Chia-Chih (Jack) Yen is the R&D Manager for the logic verification group at SpringSoft. He joined the Company in 2005 and participates in several projects in the areas of debugging and verification. Jack holds a Ph.D. in EE from the National Chiao-Tung University, Taiwan. His research interests include dynamic and static verification, testing, and logic optimization.
[Jack’s Paper Study Note] Managing Verification Error Traces with Bounded Model Debugging – Sean Safarpour et al. @ ASPDAC’10
http://www.eecg.utoronto.ca/~veneris/10aspdac.pdf Debugging is still the most time consuming part of IC design. Typical debug includes: (a) find out the checkers that indicate errors, (b) investigate waveforms of observation points (typically primary outputs) which may propagate errors to the checkers, (c) trace drivers of those observation points, (d) indicate error sources, (e) fix them, and finally [...]
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