As with last year, I will try to summarize some of the work presented in some of the User Track sessions at DAC 2010. These sessions are quite popular as it provides a forum for real users to share their findings with their peers in the industry.

I sat  in during the User Track session on Chip-Package-System power delivery network design optimization.

Sorin Dobre from Qualcomm presented how they use a comprehensive time and frequency domain methodology to design and validate their wireless chip-package-board designs.  He highlighted the complexities associated with  time domain analysis in which he includes the chip layout, package RLCK model and a fitted model for the PCB in a multi-domain analysis framework. He uses a multi-cycle resonance frequency aware VectorLess methodology to define the excitation model for his time domain analysis of this system. The current signature for the final excitation model generates high energy around the system resonance frequency stressing the chip-package-system PDN.

Davide Pandini from ST Microelectronics, Agrate, presented results on power supply noise and EMI analysis and how it can be mitigated for the chips his group designs for the automotive market. He presented in the second part of his talk the results on a case study highlighting static and dynamic voltage drop and EMI results. He illustrated how power noise from the chip propagates along the chip/package/board supply lines and radiates to the air. He highlighted a methodology of controlling the dynamic switching on the chip to control the on-die noise/drop and hence the EMI coupling.

Erhan Erglin from AMD presented a methodology of dynamic voltage drop analysis for their high performance designs targeting CPU/GPU/APU applications. He presented arguments on the need for dynamic voltage drop analysis and why inductance, both on the package and on the chip have to be included for their designs using advanced processes. As supply voltages reach threshold voltage levels, dynamic voltage drop analysis highlights areas of switching noise that can cause the chip to fail. Static IR which has been used historically is useful to find gross violations and typically show small drop (3-4% range) for their designs. But to include the package/die inductance and capacitance and the simultaneous switching current, he highlighted the need for dynamic voltage drop analysis. He presented findings showing that the inclusion of on-die inductance changes not only the peak voltage drop number, but also changes the voltage drop map.

Ricky Yong from Intel, Penang, Malaysia, presented results on power noise analysis on their MTCMOS (power gate)  designs including silicon correlation results. He focused on dynamic power noise analysis for mode transition for his power gated designs. He highlighted how they perform on-die voltage drop measurements using sense lines and showed close match between measurement and simulation results. He also presented simulation results for different power-on sequences and correlation to measurements (within 4%).

Kyung-Tae Do from Samsung presented a methodology for estimating statistical leakage and the library/modeling support needed to achieve that. He highlighted that present techniques are not applicable for large macros and that a new technique is needed. His proposed methodology uses a combination of library characterization using Monte-Carlo simulations and silicon measurement based tuning.

Souvik Mukherjee from TI, Dallas, showed results on a different but equally critical area of IO sub-system design and the impact of power ground noise on IO/memory interface timing. He mentioned that an ideal SSO/SSN analysis methodology needs to accurately trade off between accuracy and efficiency of modeling, extraction and simulation flows. He presented results using the Sentinel-SSO technology from Apache on how the PDN noise and signal cross-talk impact can be included for IO/memory interface timing analysis. He presented results using this technique and compared that to silicon measurement results for a 45nm SoC based wireless platform.

Again thanks to the various DAC committees and to all the folks who made DAC 2010 a very useful and productive show.  Headed back home now