New release of PowerCentric™ delivers 15% reductions in clock insertion delays and full support for CPF 1.1
SANTA CLARA, CA – June 14, 2010 – Azuro, Inc., the provider of advanced clock and timing optimization tools for digital chip design, today announced version 5.2 of PowerCentric™, the company’s industry-leading clock tree synthesis tool. This release deploys a proprietary new criticality-aware clustering algorithm to further reduce clock insertion delays by an average of 15% without any impact on clock power, area or skew. The product also includes full support for version 1.1 of the Common Power Format (CPF).
“As our customers migrate to 40nm and 28nm, achieving the lowest possible insertion delays is becoming critical to manage timing closure in the backend of the design flow,” said Paul Cunningham, CEO of Azuro. “But the key challenge is how to achieve these insertion delays without an unacceptable impact on power. Criticality-aware clustering uniquely blends buffering for speed with buffering for power to achieve an average of 15% reduction in clock insertion delays while at the same time maintaining our core value proposition of reduced clock power.”
CPF support in PowerCentric 5.2 follows on from the company’s announcement of its membership into the Cadence Connections program in March (see http://www.azuro.com/news/pr_2010_03_03.html). PowerCentric 5.2 is available now and is already in production use at several of Azuro’s largest customers.
About PowerCentric™
PowerCentric is a clock tree synthesis tool for digital standard cell-based chip designs. It reduces chip power by up to 20% and reduces clock area and insertion delay by up to 30%. The product also dramatically increases productivity on designs with complex re-convergent multi-mode clock networks.
About Azuro
Azuro is an electronic design automation company supplying software tools for use designing digital semiconductor chips. The company’s unique clock and timing optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held. For additional information, visit http://www.azuro.com/
Contact
Cayenne Communication – Linda Marchant, (919) 451-0776, linda.marchant@cayennecom.com
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