It’s a been while since I got a chance to write here so it seemed appropriate to update everyone on what we are doing at DAC 2010. The weather here in Anaheim has been incredibly good and with school being out lots of kids around for Disneyland so in general there is a festive spirit all around.

Lot of things happened since last time in San Francisco. The integration of the ex-Sequence team and products has happened very well. We have rolled out the next generation RedHawk™ engine (RedHawk-NX), brand new user-interface for both Totem™ and Sentinel and introduced the industry’s first layout based ESD integrity verification technology called PathFinder.

Obviously we will be talking about all our products that I list below:

• PowerArtist: for RTL level power analysis and reduction

• RedHawk: for SoC power noise and reliability analysis including CPM™ generation for chip-aware package/board analysi

• Totem: for analog/mixed signal custom design power noise and reliability analysis including substrate noise modeling, and model creation for SoC level mixed mode (cell + transistor) analysis

• Sentinel: for Chip-Package-System power, signal, EMI and thermal analysis

• PathFinder: for ESD integrity for SoC and IP designs

In addition, we have several of our customers presenting their finding and their methodologies in our booth (#535). They are:

Getting ready

• RTL power methodology (LSI)
• Foundry’s view of power integrity closure for 3D IC, 28nm, etc (TSMC)
• SRAM EM analysis and validation methodology (ST)
• Advanced VectorLess modes for dynamic voltage drop sign-off analysis (TI)
• ESD analysis for advanced IP designs (MoSys)
• IO sub-system design verification (TI)
• Package/PCB model creation with correlation to measurements
• Power and thermal variation aware design methodology (STARC)

These are in addition to several presentations our customers will have in the DAC technical sessions and User Tracks.

Hope to see you over the next few days.