3D die stacking using through silicon vias (TSVs) is an emerging technology with considerable promise in reducing the area, performance and power limitations of transmitting signals between multiple dies. It provides the flexibility of connecting chips performing different functions (memory, processor, power management) and fabricated using different processes inside the same package in a significantly closer form than what is possible in other multi-die packages like MCM’s and 3D IC’s without using TSV’s. Figure 1 illustrates several TSV based multi-die configurations. The package is not shown but connects to the bottom die for cases 1, 2, and 4 and to both dies through the silicon interposer for case 3.

The benefit of having much reduced signal transmission pathways between the stacked dies however causes considerable challenges in power delivery network (PDN) design for these connected chips. For the structures shown in figure 1, the higher level die(s) which are further away from the direct connection to the package are susceptible to noise only coming from their own switching but also are impacted from the added power noise from the die(s) below it. From pin count and routing limitations it is not always possible to isolate the PDN between the two dies both for power and for ground supply networks. Even if each die in the multi-die stack-up had its power and ground networks unique to it, the chips higher up in the stack-up will end up seeing increased power noise and voltage drop from the larger number of metal and via layers in the conduction path and from the capacitive and inductive noise coupling happening from intermediate chips. Figure 2 illustrates the increased number of metal and via layers (in addition to other structures like the TSV) that the top die in a two-die stack-up needs to encounter [1].

To mitigate the worsening of the power noise and voltage drop effects, design teams will have to focus not only on creating more robust grids for their own chips but also to ensure that the power delivery network designs done in other chips in the multi-die stack-up are adequate for their needs. They need to worry not only about the design and density of the power grid routing but also about the count, design and placement of the TSV arrays to connect the on-die power grid network to the other stacked dies. This co-design scenario is additionally impacted if the multiple chips are designed in separate companies which may not be able to share design data or may be using different design and analysis environments.

Thus a PDN analysis and optimization flow for a stacked die design needs to model the presence of multiple dies, the switching in each and the noise impact from the dies on each other. It additionally needs to consider the TSV’s and bumps that connect two stacked dies to each other. The analysis can be done in a concurrent manner in which the full design databases and layouts are simulated simultaneously (concurrent simulation). However when the different dies are being designed by different companies, such data sharing may not be possible. In that case the sharing of die models to enable a “model based simulation” has to be considered. Figure 3 shows the results using both approaches for a two die stack up. The voltage drop map shows the dynamic voltage drop on the metal 1 layers for the top die using both the approaches indicating that if sufficient attention is paid to the modeling accuracy, then the results from both a concurrent simulation (left side) and the model based simulation (right side) will be similar providing more flexibility in the way these analyses can be performed.

Thermal, signal integrity and reliability of the structures in a stacked die configurations are equally important. Any analysis looking into these areas will also have to consider the simultaneous interplay of the switching and activity of all the dies in the stacked die structure.

[1]. Internet research: Guillou, Y, “3D Integration for Wireless Products: An Industrial Perspective”, http://www.i-micronews.com/analysis/3D-Integration-wireless-products-industrial-perspective,3272.html