As a Power Integrity Experts company, we are very often called to investigate some production chip failures. Most of the time it is due to few obvious design weaknesses easily identified within RedHawk. The trouble is, those weaknesses are not detectable with a static voltage drop analysis – just between us, if a so called “static SignOff” solution was enough, we would not hear about any power integrity chip failures…

But what can of weaknesses are we talking about?
- The scan mode failure is one of the most unfortunate. As a known fact, with a static based analysis, the drop is purely proportional to the chip power consumption. Because of the slow frequencies of the scan chain(s), the average power gets smaller compared to the functional mode. But think dynamic!
In scan mode, you get most of your cells (FFs, Latches, clock buffers) switching at the same time – especially when there is only 1 single scan chain… This is the worst stressing switching scenario for your resistive PG grid and your inductive package.
Actually, since there is no way to get the PG grid designed to handle the test mode, we start to see more and more Apache users adjusting their test structures and strategies based on the corresponding dynamic analysis feedbacks.

- A second typical failure is when few set of standard cells, or even a single one, get isolated and weakly connected just because of the floorplan. The figure1 illustrates some cases.

figure1: Typical Floorplan

That’s what we use to call missing via, or impossibility to get vias as expected, at least in an automatic manner.

With a static approach, such a specific issue cannot be easily detected. A single standard cell does not consume enough average current to highlight such weakness in the static voltage drop map. But in dynamic mode, such weakness gets clearly identified.

Figure2: Supply Over TIme

Obviously, such weakness can be detected in dynamic if and only if the cell is switching during your simulation. So, even if, very luckily, you get a VCD file before your tapeout, you cannot guaranty this switching scenario will fire all those weakly connected standard cells… That’s exactly where the Apache’s Vectorless Approach will complete your analysis!
This very dedicated algorithm is automatically selecting the cells that will switch or not during your simulation. This selection is obviously dependant of the instances’ power, timing, logic, switching statistics, but it is also function of the topology of your design.  The tool identifies the weakly PG connected cells and makes them switch during your dynamic simulation. As a result, it gets very easy to viualize the consequences and quantify how bad could be the resulting dynamic voltage drop. Obviously, it is up to the designer to try different ‘what-if ‘ within RedHawk (add vias, straps or decap) in order to take the appropriate decisions,  but at least, he is aware of the weakness.

So, bottom line, if you want your chip first time right, don’t stay static and move for a dynamic solution!

Jerome