The DAC User Track is a new forum this year in DAC with lot of interesting topics. I happen to be in one of them today so wanted to share my learning from this session.

Nadeem Eleyan from Qualcomm presented a method on estimating toggle rates in their custom designs using ESP-CV instead of full Spice or Fast Spice simulations. Their method shows orders of magnitude improvement in run-time to estimate toggle activity in their designs with marginal change in results compared to Spice based methods. This power and toggle information is then used for accurate power grid noise analysis using RedHawk.

Nagata-san from Kobe University presented their study on power supply noise including substrate noise analysis and presented results on one of their test-chip designs. They used Totem-SE (Apache’s analog and substrate noise analysis solution) to perform simulations on this design and compared the results to that they saw from silicon measurements. Their work was as a result of a multi-party collaboration between STARC, Kobe University, A-R-TEC and Apache.

He highlighted two key technology contributions from this study: (a) Integrated power supply and substrate noise analysis and (b) on-chip measurement techniques. The results indicated that the inclusion of the substrate coupling and off-chip impedance are required for accurate results that match silicon.

A team from IBM presented the challenges and modeling approaches for PDN verification for multi-core designs. The approach included estimating current demand using a combination of estimated triangular and trapezoidal current waveforms to predict current at the C4 bumps.

Dr. Hwang from Samsung presented a dynamic analysis method they use for their memory designs. He highlighted some of the challenges they face (capacity, simulation run-time) and the need for accurate power noise analysis for their sensitive DRAM circuits. He presented two techniques and compared results and run-times between the methods, one detailed and one optimized. The method achieved about 15X performance improvement with less than 10% difference in results.

Siva Kothamasu from Texas Instrument presented techniques on hard IP re-use for multi-metal system SoCs. The work focused on creating hard IP designs in way that they can target multiple SoCs while allowing easy integration and debug. He outlined challenges in IP level timing closure (from consideration of additional overlap capacitance from top level routes) and showed techniques in addressing these challenges.

Thao Pham from Intel presented their work on Di/dt Mitigation Method in Power Delivery Design and Analysis.