The advancement of silicon technology and packaging, PCB technology does not happen in isolation. There is a great deal of interdependence between the IC and the interconnect world that drives technological innovation – for example, the rapid scaling of silicon and the need for high speed transmission is followed by higher performance, lower cost packages. And since there are new challenges associated with every new technological innovation, like with 3D IC packaging with TSV (through silicon vias), the chip, package and system must be designed using a co-design and co-analysis methodology. There must be increased interaction among the design communities because future product success is expected to be driven by successful system level integration – not only packing wider range of components onto a system, but also ensuring that they work well together.

There are many aspects of chip-package-system co-analysis such as signal integrity, power integrity and electromagnetic interference. For now, let’s look at the system power integrity aspect of co-analysis. The noise on the power supply is becoming a major source of noise that can cause a rail collapse, and directly impact the noise margins and the timing. The power delivery network spans multiple domains, from the VRM and through the board and package to the IO regions of the dies and all the way to the transistors on the die. At present, due to the absence of a single analysis platform that can read in the chip layouts and the package/board layouts to perform power noise simulations in one unified run, a model based approach is in-vogue. In this method, there are key ingredients: (a) comprehensive model of the chip(s), (b) accurate model of the package and board, and (c) a co-simulation platform that can take these models appropriately to perform the required simulations (frequency domain, DC, or transient). The rest of this blog discusses the die model requirements (part a) and its application in a system level analysis.

The requirements for a die model must be understood to perform an accurate system level analysis. The die must be represented with the electrical and physical properties of the chip (wires, RDL, cell/IP/macro characteristics and placement etc) and must be a compact model that contains:

(1) Current consumption profiles over different parts of the chip in a spatial and temporal sense, for every domain and at every pin.  This current signature can reflect different operating modes of the chip and can be triggered through test patterns in the form of VCDs or by using a statistical vector generation engine such as Redhawk.

(2) Parasitics present on the chip to provide an effective Rdie and Cdie which is domain specific and reflects the layout and the technology of the chip.

Such a model can be used for chip-package-system (CPS) analysis and optimization during different stages of the design cycle. In the early stages of the chip when only the power grid prototype is available, the die model can contain only the parasitic components because the chip switching activity cannot be determined. Such a model is sufficient to perform a CPS frequency domain analysis to optimize the impedance and resonance frequency points. As the chip design progresses, the die model must incorporate incremental transient current information (for DC and transient analysis ) and become an accurate representation of the die that will ultimately correlate with measurement.

There are several aspects of the power delivery network design that must be optimized and verified, such as PCB stackup, VRM placement, de-coupling capacitance selection and placement, package layer, socket and connector selection, pin assignments and placement. The basic goal is to minimize the levels of noise and the impedance over a wide frequency range while limiting the cost, size, pin count, and number of layers. To accomplish this goal, a CPS co-analysis of the following types must be performed: (1) frequency domain (2) DC and (3) transient.

In the frequency domain, the die model is used in the combined package and board analysis to study the various resonance points and compute the impedance. The resonance frequency is estimated to ensure that it does not overlap with the functional frequency of the chip and its associated harmonics. The lower frequency range resonance points are determined mostly by the PCB and package elements. However, the resonance frequency at the higher frequency range (50+ MHz) is determined by the package/PCB inductance and the die capacitance.  The chip parasitic model as mentioned earlier needs to reflect all the various capacitances present in the chip (wires, gate, diffusion, well). It also needs to model the resistance (and inductance) of the power and ground routings and the channel resistances of the devices. Additionally, an accurate parasitic model of the die can determine whether the impedance is less than the target impedance.

For DC analysis, the current drawn at various parts of the die reflect either an average or a peak current situation. The system DC analysis will reflect the average drop at the die bump locations. For time-domain analysis the complexity of this modeling is higher due to several additional requirements: a) the model must provide current profile information for sufficiently long period of time to allow for meaningful CPS time-domain analysis capturing the LC resonance effects, b) the model must reflect various operating modes of the chips providing di/dt signatures in the transitions between such modes, and c) it must be spatially distributed over the chip to capture the placement of various circuits and their operations. Various studies have been done regarding “worst casing” the current signatures.

Historically design teams have explored ways to generate such die models. But these models have typically been unable to provide the accuracy or the modeling sophistication outlined earlier.  The Chip Power Model (CPM) technology from Apache pioneered the concept of a layout driven die modeling solution that met these needs. Essentially a CPM is generated subsequent to a die level RedHawk (for digital) or Totem (for custom/analog) power noise simulations. The information (layout, library, technology parameters) provided to either RedHawk or Totem is necessary and sufficient to generate a CPM with its accuracy commensurate with the detailed nature of the data provided. The generated chip power model is an electrical representation of the layout of the chip and its operating mode in an open Spice format that can then be connected to a package model.

Today, we cannot afford to work independent of each other. Design collaboration will lead to more innovation, improved quality and lower cost. Getting a good die model in the form of CPM is a first step towards a converged chip-package-system design methodology. Stay tuned for the next posts on package/board extraction and co-simulation technologies.