Hope everyone had a great July 4th weekend. We are now three weeks away from DAC and before we know it we will be at Moscone Center. As we get ready for the conference, I wanted to share some information.

We are fortunate to have three key customers present in our booth. Harpreet Anand from Broadcom’s Mobility Group will share his experiences on using RedHawk from early in his design process to sign-off for a 45nm design and how the step by step approach helped reduce the overall design risks. Ralf Schmitt from Rambus will share his experiences on bringing up and using Totem on high speed I/O interface designs. Louis Liu from TSMC will highlight the design challenges that are prompting a move towards a SiP/3D IC based designs.

Having worked with both Ralf and Harpreet on power noise and reliability for UltraSparc processors, I know that they bring considerable experience and expertise to the work they do and their presentations not only will provide a window into the flows and methodologies they use, but also give an opportunity to understand the challenges they see confront their specific focus areas. Louis’s presentation gives us an opportunity to participate in a discussion on the issues he sees both designers and foundries face in supporting advanced SiP/3D TSV based designs. The concerns and the challenges in this are seems to be part of the keynote to be delivered by Dr. Fu-Chieh Hsu (TSMC).

Additionally there are presentations in the DAC User Track sessions covering several application areas of Apache products. Bando-san from Kobe University will share his experiences on using Totem for substrate noise analysis and silicon correlation for the same. Davide Pandini from ST Microelectronics will share his experiences of using Sentinel Chip Power/Emission Model technology for near field and far field emission study for his designs.

This year at Apache we are focusing on four key areas:

• The capacity and usability features in RedHawk-NX, which is the Next Generation RedHawk engine incorporating the Mesh Pattern Recognition (MPR) and Hierarchical Dynamic (CMM) technologies. Additionally this version of RedHawk rolls out RedHawk Explorer (RHE), which for the first time provides automated design weakness and root cause identification capabilities for power noise simulations.

• The power noise and reliability analysis capabilities in Totem covering power grid design analysis, signal electromigration and substrate noise analysis. Totem comes with a highly interactive layout editor like GUI that overlays the analysis results on the layout and highlights design weaknesses automatically allowing users to fix their designs interactively before committing to the final layout.

• The full package and board extraction support in Sentinel-PI with true 3D full-wave accuracy, its ability to read one or more die models (CPM ~ chip power models) and its flexibility to perform frequency domain, time domain and DC analyses in one integrated simulation platform.

• Co-design strategies looking at power delivery, signal noise, EMI and thermal challenges associated with integrating one or more dies in complex package structures (SiP, 3D/TSV, etc). One key area is to assess the impact of IO power noise on signal transmission and jitter. The Sentinel-SSO solution provides the ability to simulate an entire IO bank (e.g. DDR3) incorporating both power noise and signal cross-talk impact to signal propagation.

Hope you can make it to DAC. Drop by and say hi if you are around.