It is always good to start a story from the very beginning. At Apache, we are all about identifying and fixing “dynamic” voltage drop issues, and not only on the chip but also in package and board. However, before talking about Dynamic Voltage Drop it is important to understand its origins: the switching noise.

  As a matter of fact, when a chip is ‘ON’, it is meant to do something, whatever the final application. Therefore, millions of standard cells (or millions of transistors) are driving signals in a very specific way. To drive those output signals, each cell needs energy: they consume current.
When the signal is static, the cell is consuming a leakage current, which is a state dependant constant value. But when the signal is switching, the cell will consume a certain amount of current over the time. This amount of current depends on 4 main factors: the slew (transition), the charge (load), the switching direction (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) of the net and the supply voltage of the cell itself. The bigger is the net and the more aggressive is the timing, the higher will be the corresponding peak of current.
  The figures below represent the current consumption profile of a cell during a switching output event. 

This current profile is obviously also dependent of the cell structure (complexity, size). In other words, each cell, such as each transistor, does have its own characteristics depending of the output signal.

Note:  It is important to notice that the frequency of the net does not directly change the value of the peak of current but rather the frequency of this peak. In other words, the frequency is impacting the “average” current consumption (better known as “average power”).

It is mandatory for a tool such as RedHawk to perfectly understand and use these current profiles in a way that mimics their physical operation (e.g. the current draw should depend on the supply voltage to that transistor) to compute an accurate Dynamic Voltage Drop.  Since the chip is not only made of standard cells but includes also memories, analog and full custom IPs, it implies a wide range a different current profiles for each element. So far we store all those profiles in APL (Apache Power Library) format. This is a spice based characterization; we may develop a bit more this subject later in this blog.

So, a cell needs current to drive a net - fine - but we may wonder why we hear more and more about switching noise with the last new technologies. As matter of fact, since we are shrinking a lot the geometries, the output loads and the cells get reduced, and therefore the corresponding switching peak of current. On the other hands, still due to this shrinking, we end up with much more transistors and cells per mm². In other words, the issue is not coming from individual current cell consumptions but from thousands of cells that are potentially switching at the same time in a very small area of your die. The density increases faster than the peak of current reduction. The real source of noise is clearly a simultaneous switching matter.

Even if today some technics such as gated clocks or skew and phase control tend to limit the simultaneous switching events, the transistor density gets so high, that we have to control the switching current and hence the switching noise very carefully. Additionnally, the tight design requirements on the chip, its package and its board make it more difficult to supply these high switching current requirements quickly enough. Thus, we see increasing needs for co-design solutions like Sentinel and RedHawk for designers working on advanced technology designs.