Last week I was visiting our customers in various locations in Israel. In many ways this trip was important. We had just announced Totem™, our full-chip transistor level power noise and reliability analysis solution which many of our users in Israel have been using for some time. We were seeing increased acceptance of our co-design methodology among our world-wide system and semiconductor customers and many of our Israel customers had provided important feedbacks in defining this methodology.

The many beautiful places our users live and work.

The most common question I get prior to visiting Israel is if it’s safe. I have never felt otherwise. I have walked in the ancient streets in Jaffa or gone running along the Promenade in Haifa late at night and never felt insecure or concerned. On the other hand, the visits are extremely fruitful not only in understanding how our many products are used but also from the insightful feedbacks I get from all the design teams we engage in. Our users in Israel, either from their work on some of the most advanced and complex designs or from their focus on having the most price competitive product, have adopted our power noise analysis solutions in comprehensive manner using them not only in the flow we recommend but also by adapting it to their specific needs by working closely with our local and world-wide application engineering and RnD teams.

While RedHawk™ use for the SoC or digital circuit analysis has been wide-spread since we started working with our customers there, the visit offered tantalizing insights into how our customers have obtained considerable value from using our Totem™ solution on their taped-out or ongoing designs. They have used it to validate the IPs they obtain from internal or external design teams to highlight issues that the traditional netlist based flows that the IP design teams use have missed. They have also been able to simulate entire designs or blocks that they had to earlier partition and simulate either in pieces or partially. They have also benefitted from Totem’s integrated simulation driven signal line electromigration analysis for their advanced sub-65nm designs.

Quite a few of our customers there have had co-design methodologies, but our CPM™ (Chip Power Modeling) and Sentinel-PI technologies have given them an accurate, usable and robust framework to perform their chip-package-board co-simulations and design changes. The use of CPM in a model based design environment (one in which models of the package, board and die are cascaded and simulated in a Spice simulator) tend to have complexities especially if the package model is in the S-parameter format or Broadband Spice models which do not reflect the physical nature of the CPM netlist. Discussions of model based simulation flows with our users in Israel tend to revolve around the parameters used to generate the CPM in a manner that makes it most suitable for a hook-up to such package models and the feedbacks from our customer in Israel have helped clarify some of those questions. Other discussions revolve around the various simulation scenarios that can be used to create a CPM to make the combined chip-package-board transient analysis representative of various operating modes of the system.

Interest in Sentinel-PI continues to build up given the benefits it provides. Sentinel-PI first imports the die model (CPM) along with the package and board layouts. It performs circuit level connection (die bump to package bump, package ball to board solder) and performs an integrated analysis (DC, AC, transient or EMI) within a single environment. Thus, users not only benefit from Sentinel-PI’s true 3D full-wave modeling accuracy but also from its proper handling of die to package to board connections resolving inaccuracies or ambiguities that arise in a cascaded model based approach. Due to their work on high speed, sensitive circuits or from a need to control the design margins and the costs across these disparate domains, our customers appreciate Sentinel-PI’s value proposition. Many of our users benchmark Sentinel-PI against HFSS taking small representative circuits while others have qualified it against measurements. Those results have increased their confidence in using Sentinel-PI to extract their entire package and board layouts with 3D full-wave accuracy (which they are unable to do in other available 3D full-wave extraction tools) and to leverage its unified simulation environment. Hence I look forward to my next visits there to get feedback on their experience on using Sentinel-PI.

On a separate note, I am very thankful to one of our users in Haifa, who introduced us to Pichoto, a fabulous find in Zikhron Ya’akov. I will recommend it to any of the readers who happen to visit Haifa and are looking for a place to have dinner of local favorites paired with fabulous local wines.

Till next time, cheers or as my colleagues in Israel would say, L’Chaim.