We have been working on the power-aware related projects for a while and there are some interesting experiences and thoughts that we would like to share in several blog posts. Hope you will enjoy it and please feel free to give us feedback.

As we all know, low-power has become a more, if not the most, important design constraint over the past few years. Mobile devices such as iPhones/iPods are getting so popular that people want to use them all the time. Although the battery techniques have improved dramatically, effective power management, either in software or hardware, is still the key to keeping the power consumption under control. There are several techniques in hardware power management such as power-shutoff (PSO) and dynamic voltage scaling (DVS). Both techniques have shown to be very effective to reduce both dynamic and leakage power.

Power management is usually planned in the RTL or even an earlier architecture stage. To design power management in the RTL stage, new languages called Power-Definition-Markup-Language PDML (such as CPF and UPF), are used to compensate the lack of power modeling capability in traditional HDL. Similar to HDL, CPF/UPF describes hardware functionality but only focuses on the power related parts. Designers can use CPF/UPF to specify the power-domain, power-shutoff condition, level-shifter, isolation and retention strategy. The HDL simulator then takes both HDL and CPF/UPF as inputs and imposes the power introduced behavior during the simulation run. For example, if a component is power-shutoff at particular time during simulation, the HDL simulator will cancel all corresponding events and assign its value to unknown. By co-simulating both HDL and PDML, designers can verify the design behavior with power-intent.

Since CPF or UPF are usually designed and written manually by a designer, it will be error prone just like any software. Moreover, since CPF and UPF interact with the HDL design, debugging them together can be very tricky. We called this type of debugging process as power-aware debugging.

Before getting into what power-aware debugging is and why it is so important, we would like to share some of our observations between the two mainstream power-definition-markup-languages – UPF and CPF. Although we haven’t been involve in the UPF or CPF development since the very beginning, we have followed their progress very closely. Both languages have been evolving over several versions in the past two years. UPF is in the process of becoming an IEEE standard (P1801) and CPF is still keeping itself as an open language.

Although both languages try to achieve the same thing – description of power intention – both languages actually have very different design philosophies in mind. UPF is more like a “structure” language which is used to describe the physical “power network”. You need to define the power-source, the corresponding supply voltage, the power supply-net, and the power-switch. The power-intent is then described as the power-network. If you want to design a dynamic voltage scaling (DVS) system, you need to define a set of power-supplies with different supply voltages. Then you have to connect the supply source to power-switch via power supply-net and defines the control condition of the power-switch to make it provides the corresponding voltage under certain control configurations. This process is very similar to constructing a Netlist with HDL language.

CPF, on the other hand, is more like a “behavior” description language. The on/off condition and the voltage status can be described as simple behaviors. For example, to implement DVS, you have to define the power-state-table and the corresponding state transitions. Each power-state represents which region (power-domains) is supplied by what voltage value.