As with last year, I will try to summarize some of the work presented in some of the User Track sessions at DAC 2010. These sessions are quite popular as it provides a forum for real users to share their findings with their peers in the industry. I sat in during the User Track session [...]
Mark Waller![]() |
![]() |
![]() |
Custom chip designers are reluctant to adopt automation, largely because they have been traditionally better able to design by hand. While hand crafting may still suffice for designs of relatively few transistors, it is no longer sufficient for the new, highly complex devices that are becoming the norm. At advanced nodes, process rules make full [...]
Read More
http://www.eecg.utoronto.ca/~veneris/10aspdac.pdf Debugging is still the most time consuming part of IC design. Typical debug includes: (a) find out the checkers that indicate errors, (b) investigate waveforms of observation points (typically primary outputs) which may propagate errors to the checkers, (c) trace drivers of those observation points, (d) indicate error sources, (e) fix them, and finally [...]
Read More
While many of us are just getting used to writing “2010” on our documents and personal checks, it’s clear that the economic impact of 2009 will not be forgotten any time soon. The consensus across diverse constituencies – ranging from world leaders to industry heads and many leading economists – is clear. We are not [...]
Read More
Fernando Martinez Vallina
Twitter FeedsPosting tweet...