Is there a disconnect in your die, package and board design methodology? As technologies evolve to meet demands of higher performance, smaller size and lower cost, there are several challenges in the design of chips, packages and boards which must be addressed with an integrated analysis and verification methodology. For example, maintaining power integrity means ensuring [...]
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3D die stacking using through silicon vias (TSVs) is an emerging technology with considerable promise in reducing the area, performance and power limitations of transmitting signals between multiple dies. It provides the flexibility of connecting chips performing different functions (memory, processor, power management) and fabricated using different processes inside the same package in a [...]
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As pointed out in the previous post, a not-well-verified IP can be a major killer for any SoC project. SoC integrators basically don’t have the time or resources to debug individual problematic IPs. A bad IP can really delay a project, if not kill it. Having a robust IP signoff process is really critical and adopting [...]
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